[问答]

模拟Xilinx CAM失败

3356 CAM

问答对人有帮助，内容完整，我也想知道答案 0 我使用了“xapp1151”CAM设计，并使用提供的perl脚本对其进行了定制。它在ISE中合成没有错误，但是当涉及到模拟时会出现问题。由于以下错误，在ModelSim 10.0C或Isim 14.2中模拟此核心失败。似乎两个阵列具有不同的长度，因此模拟失败。请告诉我如何解决此问题。我应该补充说，更改两个向量长度并不是一件容易的事，因为要配置的参数太多。只是提醒你，这个CAM不是我自己的设计。我只是使用可用的脚本定制它。我的配置：cam_depth = 16，cam_width = 48，二进制编码地址。在此先感谢.ModelSim错误：＃致命:( vsim-3420）数组长度不匹配。左边是36（35下降0）。右边是72（71下降0）。＃时间：0 ps迭代：0实例：/ test_ram_cam / u_cam_wrapper / top_cam / rtl_cam / mem / gblk / blkmem / gextw（0）/ gcp / extd / gextd（0）/ gincp / extdp / s6prim / BRAM_TDP_MACRO_inst / ramb_st / ramb18_dp_st / ram18_st文件：C：/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd行：599 #Datal ERROR加载设计时 Isim错误：HDLCompiler：410 - “N：/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd”第599行：表达式有72个元素; 预期36ERROR：模拟器：777 - 图书馆工作中顶级VHDL设计单元test_ram_cam的静态细化失败以上来自于谷歌翻译以下为原文 I used "xapp1151" CAM design and customized it using presented perl scripts. It synthesizes without errors in ISE, but when it comes to simulation a problem arises. Simulating this core in either ModelSim 10.0C or Isim 14.2 fails due to the following errors. It seems that two arrays have different lengths, hence simulation fails. Please tell me how to resolve this issue. I should add that changing the two vector lengths is not an easy task, since there are too many parameters to be configured. Just to remind you, this CAM is not my own design. I just have customized it using available scripts. My Configurations: cam_depth = 16, cam_width = 48, Binary Encoded Address. Thanks in advance. ModelSim Error: # Fatal: (vsim-3420) Array lengths do not match. Left is 36 (35 downto 0). Right is 72 (71 downto 0). # Time: 0 ps Iteration: 0 Instance: /test_ram_cam/u_cam_wrapper/top_cam/rtl_cam/mem/gblk/blkmem/gextw(0)/gcp/extd/gextd(0)/gincp/extdp/s6prim/BRAM_TDP_MACRO_inst/ramb_st/ramb18_dp_st/ram18_st File: C:/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd Line: 599 # FATAL ERROR while loading design Isim Error: HDLCompiler:410 - "N:/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd" Line 599: Expression has 72 elements ; expected 36 ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test_ram_cam in library work failed 0
2019-2-28 13:46:51　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答举报李蒙相关推荐 • 通过ISim模拟HDL代码出现错误 1466 • XILINX ISE 11.1安装正确但不能模拟ISIM 3699 • 如何用Verilog HDL设计CAM？ 2567 • XILINX_AXI_BFM许可证检索失败 2726 • 如何将esp32 cam连接到万用表？ 313 • 如何将esp32 cam连接到万用表？ 133 • 请问在cam350中如何将cam文件转换为gerber文件？ 7903 • xilinx 13.4错误导致编译失败 1476 • cam文件检错 3189 • PADS9.3 怎样转CAM350 5913 1个回答

答案对人有帮助，有参考价值 0 msjatxilinx写道：我使用了“xapp1151”CAM设计，并使用提供的perl脚本对其进行了定制。它在ISE中合成没有错误，但是当涉及到模拟时会出现问题。由于以下错误，在ModelSim 10.0C或Isim 14.2中模拟此核心失败。似乎两个阵列具有不同的长度，因此模拟失败。请告诉我如何解决此问题。我应该补充说，更改两个向量长度并不是一件容易的事，因为要配置的参数太多。只是提醒你，这个CAM不是我自己的设计。我只是使用可用的脚本定制它。我的配置：cam_depth = 16，cam_width = 48，二进制编码地址。在此先感谢.ModelSim错误：＃*致命:( vsim-3420）数组长度不匹配。左边是36（35下降0）。右边是72（71下降0）。＃时间：0 ps迭代：0实例：/ test_ram_cam / u_cam_wrapper / top_cam / rtl_cam / mem / gblk / blkmem / gextw（0）/ gcp / extd / gextd（0）/ gincp / extdp / s6prim / BRAM_TDP_MACRO_inst / ramb_st / ramb18_dp_st / ram18_st文件：C：/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd行：599 #Datal ERROR加载设计时 Isim错误：HDLCompiler：410 - “N：/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd”第599行：表达式有72个元素; 预期36ERROR：模拟器：777 - 图书馆工作中顶级VHDL设计单元test_ram_cam的静态细化失败好吧，生活有时并不容易，但错误信息很明确，它告诉你如何解决问题。 ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 msjatxilinx wrote: I used "xapp1151" CAM design and customized it using presented perl scripts. It synthesizes without errors in ISE, but when it comes to simulation a problem arises. Simulating this core in either ModelSim 10.0C or Isim 14.2 fails due to the following errors. It seems that two arrays have different lengths, hence simulation fails. Please tell me how to resolve this issue. I should add that changing the two vector lengths is not an easy task, since there are too many parameters to be configured. Just to remind you, this CAM is not my own design. I just have customized it using available scripts. My Configurations: cam_depth = 16, cam_width = 48, Binary Encoded Address.* Thanks in advance. ModelSim Error: # * Fatal: (vsim-3420) Array lengths do not match. Left is 36 (35 downto 0). Right is 72 (71 downto 0).* # Time: 0 ps Iteration: 0 Instance: /test_ram_cam/u_cam_wrapper/top_cam/rtl_cam/mem/gblk/blkmem/gextw(0)/gcp/extd/gextd(0)/gincp/extdp/s6prim/BRAM_TDP_MACRO_inst/ramb_st/ramb18_dp_st/ram18_st File: C:/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd Line: 599 # FATAL ERROR while loading design Isim Error: HDLCompiler:410 - "N:/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd" Line 599: Expression has 72 elements ; expected 36 ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test_ram_cam in library work failed Well, life sometimes isn't easy, but the error message is clear and it tells you exactly how to fix the problem. ----------------------------Yes, I do this for a living.

2019-2-28 14:01:38 评论举报黄淳