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大家好。
当我处理我的项目时，我发现了一个问题如下。 我的DDR3应用程序端口为200 MHz，另一个内存控制器为100 MHz。 DDR3和控制器之间有一个DMA。 我曾经认为我可以使用200 MHz进行DMA设计。 但是DMA和控制器之间的接口并不容易。 特别是发送和接收数据和cmd的时间。 我在论坛上搜索相同的帖子但未找到。 有什么建议吗？ 谢谢。 以上来自于谷歌翻译 以下为原文 Hi, all. When I work on my project, I find a problem as follow. My DDR3 app port is 200 MHz and another memory controller is 100 MHz. There is a DMA between the DDR3 and the controller. I once think that I can use 200 MHz for the DMA design. But the interface between DMA and the controller is not that easy to be done. Especially the timing when sending and receive data and cmd. I've search the forum for the same thread but not found. Is there any advice? Thanks. 
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6个回答
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由于我使用DCM，100MHz和200MHz电路来自同一个源。
很好，那么你真的没有完全异步的时钟域。 实际上，200MHz侧可以将100MHz信号视为处于同一域中，并且每隔一个周期禁用时钟。 使用时钟启用，你会没事的。 请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Since I use the DCM, 100MHz and the 200MHz circuits are from the same source.Excellent, then you don't really have completely asynchronous clock domains. In fact, the 200MHz side can treat the 100MHz signals as if they were in the same domain, with the clock disabled every second cycle. Use clock enables and you will be fine. Please google your question before asking it. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).View solution in original post |
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我不认为FIFO可以解决问题，因为不仅有数据而且还有cmd。
而整个设计将需要太多的FIFO。 由于DMA具有用于缓存的BRAM，因此听起来更复杂。 我想知道是否必须将系统时钟整合到100 MHz。 唯一的问题是控制器是由其他人编写的，而不是我。 以上来自于谷歌翻译 以下为原文 I don't think FIFO can solve the problem as there is not only data but also cmd. And the whole design will call for too many FIFOs. As the DMA has a BRAM for caching, things sounds more complex. I wonder if I have to unit the system clock into 100 MHz. The only problem is that the controller is written by others, not me. |
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我不认为FIFO可以解决问题，因为不仅有数据而且还有cmd。
“cmd”也只是位和字节，所以问题出在哪里？ 您可以使用跨越相同时钟域的多个FIFO，只需记住您在同一周期中推送的两个单词不一定同时到达。 或者，您可以从同一源为100MHz和200MHz电路提供时钟。 你的情况可行吗？ 请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。 以上来自于谷歌翻译 以下为原文 I don't think FIFO can solve the problem as there is not only data but also cmd."cmd" ist also just bits and bytes, so where is the problem? You can use several FIFOs crossing the same clock domains, just remember that two words which you push in the same cycle don't necessarily arrive at the same time. Alternatively, you can clock the 100MHz and the 200MHz circuits from the same source. Is that feasible in your case? Please google your question before asking it. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left). |
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感谢您的回复。
是的，cmd也是字节。 我没说清楚。 我担心的是接口信号。 例如，控制器和DMA在发送和接收cmd时需要震动。 这就是问题所在。 由于时钟频率不同，我必须保持信号从DMA到控制器两个周期。 否则，控制器无法接收它。 那就是问题所在。 此外，当控制器发送一个100 MHz的cmd，并且DMA以200MHz接收它时，它似乎得到两个相同的数据。 我想知道我是否描述了我遇到的问题。 由于我使用DCM，100MHz和200MHz电路来自同一个源。 以上来自于谷歌翻译 以下为原文 Thanks for your reply. Yes, the cmd is also bytes. I didn't say it clearly. What I worry about is the interface signals. For instance, the controller and DMA need to shockhand when sending and receiving cmd. Here comes the problem. As the clock frequences are different, I has to keep the signal for two cycles from the DMA to the controller. Otherwise, the controller cannot receive it. That's the problem. Also, when the controller sends a cmd with 100 MHz, and DMA receives it with 200MHz, it seems to get two same data. I wonder if I describe the problem I met clearly. Since I use the DCM, 100MHz and the 200MHz circuits are from the same source. |
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由于我使用DCM，100MHz和200MHz电路来自同一个源。
很好，那么你真的没有完全异步的时钟域。 实际上，200MHz侧可以将100MHz信号视为处于同一域中，并且每隔一个周期禁用时钟。 使用时钟启用，你会没事的。 请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。 以上来自于谷歌翻译 以下为原文 Since I use the DCM, 100MHz and the 200MHz circuits are from the same source.Excellent, then you don't really have completely asynchronous clock domains. In fact, the 200MHz side can treat the 100MHz signals as if they were in the same domain, with the clock disabled every second cycle. Use clock enables and you will be fine. Please google your question before asking it. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left). |
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感谢您的快速答复。
我将搜索异步时钟域相关主题，看看我是否可以自己解决问题。 无论如何，再次感谢。 以上来自于谷歌翻译 以下为原文 Thank you for your quick reply. I will search for the asynchronous clock domains related topic and see if I can solve the problem by myself. Anyway, thanks again. |
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