在外部引脚和ADC之间是否需要缓冲？

我想1是用于多路AMUX两VX和IX的你有TIA输入
来自它。
也没有问题，amux1输出坐在由于反馈在TIA的参考？
Eg. TIA是一个追随者的VREF，将其输入在2.5？
问候，Dana。



     以下为原文
  I presume AMUX 1 is being used to mux both Vx's and Ix's as you have the TIA input
    coming from it.
     
    Also is there not a problem that AMUX1 output sits at Vref due to fdbk around TIA ?
    Eg. TIA is a follower to Vref, which puts its inv input at 2.5 ?
     
    Regards, Dana.

一个快速的SPICE仿真证实了早期后（注意运放= 500 mV）—



     以下为原文
  A quick spice simulation to confirm earlier post (note OpAmp out = 500 mV) -
     
   

应该提到这第一次发帖，TIA作为反相运算放大器时，其混合在。外部引脚将被连接到一个电阻传感器再到地面，使节点被拉到VREF绘制电流根据电阻的变化。



     以下为原文
   Should have mentioned this in the first post, the TIA is being used as an inverting op amp when its muxed in.  The external pin will be connected to a resistive sensor and then to ground, so that node being pulled to vref is drawing a current according to the change in resistance.  

那么为什么不消除OpAmp和AMUX2，只是添加一个输入到AMUX1的TIA？
或者，如果使用TIA有几个，但不是全部，AMUX1输入，仅仅消除OpAmp，不需要
对于它，因为它有更多的漂移和偏移误差。
问候，Dana。



     以下为原文
  Then why not eliminate OpAmp and AMUX2 and just add an input to AMUX1 for the TIA ?
     
    Or if using TIA with several, but not all, AMUX1 inputs, just eliminate OpAmp, no need
    for it, as it contributes more drift and offset error.
     
    Regards, Dana.

ICANT摆脱Opamp，它不会编译没有块在那里。当我有一个MUX公共连接到任何其他AMUX时，它会出错。应该能够将8个输入中的任何一个连接到TIA。我想我已经决定用两个SARS而不是使用单一的SAR。



     以下为原文
  I cant get rid of the Opamp, it wont compile without a block there.  It errors when I have a mux common connected diirectly to any other amux.  I need to be able to connect any of the 8 inputs to the TIA.  Think i have just settled on using two SARs instead of using a single SAR.  

你好，
你不必浪费一个单位增益PGA，因为你面临的错误是连接一个AMUX的输出到另一个。
这里有一个简单的方法来摆脱它。
1。断开AMUX1和AMUX2的输出之间的连接。
2。在两者之间放置一个“网领带”组件。现在，“网络领带”组件将充当AMUXY1的输出与AMUXY2的输入之间的中介。
三。在Auxx1的输出和网络绑定组件之间的网络上放置一个网络约束组件，并将其配置选择为AMUXBUL。
4。同样，放净净的领带约束构件组件和amux_2的输入和选择是amuxbusr配置之间的线。
5。现在，如果你构建了这个项目，你就不会面临任何错误。
进一步的参考，我附上截图如何“顶层设计。cysch”看起来。
问候，Asha
阿姆苏溶液
44.3 K



     以下为原文
  Hi,
    You need not waste a unity gain PGA because of ther error you are facing by connecting the output of one AMUX to another.
    Here is an easy way to get rid of it.
    1. Break the connection between the output of AMUX_1 and AMUX_2.
    2. Place a "Net Tie" component between the two. Now, the "Net Tie" component would act as a mediator between the output of AMUX_1 and the input of AMUX_2.
    3. Place a net constraint component on the wire between AMUX_1's output and the net tie component and select its configuration to AMUXBUSL.
    4. Similarly, place a net constraint component on the wire between net tie component and AMUX_2's input and select its configuration to be AMUXBUSR.
    5. Now if you build the project, you will not face any error.
    For further reference, I have attached a screenshot of how the "TopDesign.cysch" would look.
    Regards,
Asha

•   AMUX_solution.png 44.3 K