时间限制无法满足问题

您不会通过设置环境变量来解决问题，但是您将允许Map
完成所以你可以得到一个完整的时间报告，显示失败的路径。
没有
没有办法调试问题。
对于所需的时钟周期，您可能有太多的逻辑级别，或者您
有一些时钟交叉点被工具不必要地限制。
没有
至少一张后映时序报告，你不知道是哪种情况。
底线，设置变量，让地图完成并查看发布地图报告
失败的路径。
然后决定是否需要修复路径或添加约束
别理他们。
-  Gabor
-  Gabor



以下为原文

You will not fix the problem by setting the environment variable, however you will allow Map
to complete so you can get a complete timing report that shows the failing paths.  Without
that there is no way to debug the issue.
 
It is possible that you have too many levels of logic for your required clock period, or you
have some clock crossings that are being unnecesssarily constrained by the tools.  Without
at least a post-map timing report you don't know which is the case.
 
Bottoms line, set the variable, let map complete and look at the post map report to find
the failing path(s).  Then decide whether you need to fix the paths or add constraints to
ignore them.
 
-- Gabor
-- Gabor

嗨，
谢谢回复。
我需要在哪里设置这个env变量，以便我可以完成地图和P＆amp; R？
感谢致敬，
Z.



以下为原文

Hi,
 
Thanks for the reply. Where do I need to go to set this env variable so that I can complete the map and P&R?
 
Thanks and regards,
Z.

我需要去哪里设置这个env变量，以便我可以完成地图和P＆amp; R？
如何执行此操作取决于操作系统。
为什么不在网上搜索这些信息？
您想要搜索帮助吗？
使用最新版本的ISE，Navigator GUI不依赖于环境变量。
您准备好将您的古代ISE 10.1更新到更新版本吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Where do I need to go to set this env variable so that I can complete the map and P&R?
 
How to do this depends on the operating system.
Why not search the web for this information?  Would you like help with the search?
 
With the more recent versions of ISE, the Navigator GUI does not depend on environment variables.
Are you ready to update your ancient ISE 10.1 to a newer version?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

如果您正在使用WIndows，我建议您下载Rapid Environment Editor：
http://www.rapidee.com/en/history
这使得管理环境变量变得更加容易。
-  Gabor
-  Gabor



以下为原文

If you're using WIndows, I'd suggest downloading the Rapid Environment Editor:
 
http://www.rapidee.com/en/history
 
This makes it much easier to manage your environment variables.
 
-- Gabor
-- Gabor

喜
感谢回复，我能够设置env变量并生成位文件。
bitfile看起来运行正常，但在设计摘要中，我有2个失败的约束。
我已将报告附在帖子上（timing_report.jpg）。
前两个约束没有得到满足。
我不确定报告是否表明设置或保持时间失败。
如果是，我怎么解决它们？
我应该删除约束吗？
任何输入对我都有很大的帮助。
谢谢。
ž。



以下为原文

hi,
 
thanks for the replies, i was able to set the env variable and make the bitfile. the bitfile looks to run properly, but in the design summary, i have 2 failing constraints. i have attached the report to the post (timing_report.jpg). 
 
the first 2 constraints are not being met. I am not sure if the report indicates a setup or hold time failure. and if it is either, how can i resolve them? should i just remove the constraint?
 
any inputs for this will be of great help to me.
 
thanks.
z.

您需要创建一个详细的时序报告，以查看单独的失败路径并做出决定
这些是否真的存在问题。
失败的两个约束都是设置问题（负松弛仅在SETUP行上）。
它们似乎也是PERIOD约束，但这并不一定意味着失败
路径不跨越时钟域。
您需要查看报表查看器中的失败路径，
这将显示源和目标时钟。
如果路径跨越您认为不相关的时钟域（即使它们
可以通过DCM或PLL从相同的时钟输入生成，然后您可以忽略
他们。
如果路径在源和目标的同一时钟上，那么您需要检查这些
路径可以安全地传输多个时钟周期，如果是，则创建多周期
“FROM：TO”限制他们。
如果不是这种情况，那么你需要仔细研究设计并解决方法
帮助它跑得更快。
在论坛中搜索“时序收敛”以帮助解决此类问题。
-  Gabor
-  Gabor



以下为原文

You need to create a Verbose timing report to see the individually failing paths and decide
whether these are actually problems or not.
 
The two constraints that fail are both setup issues (negative slack is only on the SETUP line).
They also appear to be PERIOD constraints, but that doesn't necessarily mean that the failing
paths don't cross clock domains.  You need to look at the failing paths in the report viewer,
which will show source and destination clocks.
 
If the paths are crossing clock domains that you consider to be unrelated (even though they
may be generated from the same clock input via DCM or PLL), then you may be able to ignore
them.
 
If the paths are on the same clock for source and destination, then you need to check if these
paths can safely take more than one clock period to propagate, and if so create multicycle
"FROM : TO" constraints for them.
 
If none of these are the case, then you need to look closely at the design and decude how to
help it run faster.  Search the forums for "timing closure" to help with this sort of issue.
 
-- Gabor
-- Gabor