什么是时间限制

嗨，
我不确定时间限制到底是做什么的。
例如，OFFSET OUT AFTER-在这种情况下，存在来自下游设备的输入时钟。
从FPGA到此下游设备的所有数据传输都应在此时钟的上升沿。
时钟周期为30ns，建立时间为10ns。
AFTER约束基本上表示从输入时钟到达输入引脚的时间到数据熄灭的时间的最大时间，时钟的上升沿可以是约束中指定的时间的最大值。
这看起来不是设置时间。
它也不是时候。
如何使用此AFTER约束指定设置和保持时间
其次，约束是否会影响pAR？
我正在读，它只是检查并且实际上没有改变PAR中的任何内容。
告诉别人请告诉我？



以下为原文

Hi,

I am a little unsure of what exactly the timing constraints actually do. For example the OFFSET OUT AFTER- IN this case there is an input clock coming from an downstream device. All data transfer from the FPGA to this downstrea device is to be on the rising edge of this clock. The clock period is 30ns, and the setup time is 10ns. The AFTER constraint basically says the maximum time from the time the time the input clock arrives on the input pin to the time the data goes out with the rising edge of the clock can be a maximum of the time specified in the constraint. This doesnt look to be setup time. It isnt hold time either. How do I specifiy the setup and hold times using this AFTER constraint

Second, does the constraint affect pAR? I was reading that it is only to check and doesnt actually change anything in the PAR. COuld someone please let me know?