通过MATLAB中的UART从FPGA板读取数据不是连续的1到6

嗨，
这可能有很多原因。
你如何处理BRAM？
您使用的操作系统和硬件是什么？
（Matlab的串行对象在所有组合中都不能正常工作）
除了UART和BRAM之外，你的设计还有什么？
有一个很好的综合 
Eilert



以下为原文

Hi,
this can have a number of causes.
 
How do you address the BRAM?
What OS and Hardware are you using?
(the serial object of Matlab does not work properly with all combinations)
 
What else is in your design but a UART and a BRAM?
 
Have a nice synthesis
  Eilert

你好Eilert
感谢您的回复，以下是有关设计的详细信息。
你如何处理BRAM？
signal my_addr_counter：std_logic_vector（5 downto 0）;
add_gen_process：进程（CLOCK）开始if（rising_edge（CLOCK））然后my_addr_counter结束if; end process add_gen_process;
Memory_In：My_Memory端口映射（clka => CLOCK，ena =>'1'，wea => wea_null，addra => my_addr_counter，dina => dina_null，douta => douta）;
您使用的操作系统和硬件是什么？
我在我的电脑上使用Windows XP和Matlab 2009。
和Spartan 6 FPGA（xc6slx45）ATLYS板。
除了UART和BRAM之外，你的设计还有什么？
我只是从BRAM读取数据并提供给UART。
我只是检查通信，在成功实现之后，我将从BRAM处理数据，然后处理后的数据将通过UART进入PC。
Thankx



以下为原文

Hello Eilert
Thankx for your reply, followings are the details about the design.
 
How do you address the BRAM?
 
signal my_addr_counter: std_logic_vector(5 downto 0);
 
add_gen_process : process (CLOCK)
begin
if (rising_edge(CLOCK)) then
my_addr_counter <= std_logic_vector( unsigned(my_addr_counter) + 1);
end if;
end process add_gen_process;
 
Memory_In : My_Memory
port map (
clka => CLOCK,
ena => '1',
wea => wea_null,
addra => my_addr_counter,
dina => dina_null,
douta => douta
);
 
What OS and Hardware are you using?
I am using Windows XP, and Matlab 2009 on my PC. And Spartan 6 FPGA (xc6slx45) ATLYS board.
 
What else is in your design but a UART and a BRAM?
I am just reading the data out from BRAM and feeding to UART. I just checking communication, after the successfull implementation of this I am going to process data out from BRAM and then the processed data will go to PC via UART.
 
Thankx
 

嗨，
由于ATLYS板上有一个USB串行转换器，因此UART通信应该可以正常工作。
如何防止超越UART FIFO？
你用于地址计数器和BRAM的时钟频率是多少？
由于您的计数器遍历所有地址并且RAM将相应数据提供给UART-TX，因此您可能会使用数据超出UART，因此您只会收到一些有趣的欠采样模式的实际数据流。
您应该对设计进行简单的模拟，以查看来自RAM的数据以及UART-TX模块发出的数据。
另外，如果有UART FIFO的标志，请查看它们的标志。
顺便问一下，您使用的是哪种UART（IP）？
有一个很好的综合 
Eilert



以下为原文

Hi,
since the ATLYS board has a USB-Serial converter on board the UART communication should work.
 
How do you prevent overrunning the UART FIFO?
What's the clock rate you are using for the address counter and BRAM?
 
Since your counter cycles through all adresses and the RAM gives the according data to the UART-TX it might be that you are overrunning the UART with data and so you just receive some funny undersampled pattern of the real data stream.
 
You should do a simple simulation of your design, to see the data coming from the RAM and what is sended by the UART-TX module. Also, take a look at the flags of your UART FIFO if there is one.
 
By the way, which UART (IP) are you using?
 
Have a nice synthesis
  Eilert
 

你好
我试图模拟设计以检查来自Block内存的o / p。
在模拟时，我删除了UART部分。
但是当使用我可用的两种模拟器，即ISIM和ModelSim XE时，两者都给出如下的o / p
---------------------------------------
ISIM
---------------------------------------
在ISIM中，它只显示第一个内存位置包含，因为，生成地址的以下行，我认为不起作用。
my_addr_counter
ISIM给了我以下警告，所以my_addr_counter始终保持为“xxxxxx”
在5 ns（1），Instance / test_bram_mem / uut / Memory_In / U0 / mem_module /：警告：在算术操作数中有一个'U'|'X'|'W'|'Z'|' - '，
结果将是'X'（es）。
---------------------------------------
ModelSim XE III / Starter
---------------------------------------
ModelSim不会找到与之兼容的filexilinxcorelib.blk_mem_gen_v4_3.vhd。
＃ - 编译my_memory的架构my_memory_a＃**错误：（vcom-11）找不到xilinxcorelib.blk_mem_gen_v4_3。＃**错误：ipcore_dir / my_memory.vhd（66）:( vcom-1195）找不到扩展名“xilinxcorelib
.blk_mem_gen_v4_3" 。
--------------------------------------------------
--------------------------------------------------
-----
您能否建议我使用任何其他方式进行检查或在哪里可以获得与ModelSim XE III兼容的xilinxcorelib.blk_mem_gen_v4_3.vhd（我在xilinx.com上找不到它）。
请给我指导。



以下为原文

Hi
I tried to simulate the design to check to o/p from Block memory. While simulating, I removed the UART part. But while using both simulators which are available with me i.e. ISIM and ModelSim XE, both give o/p as follows
---------------------------------------
ISIM
---------------------------------------
In ISIM, it shows only first memory location contains, because, the following line which generates the address, I think not working. 
my_addr_counter <= std_logic_vector( unsigned(my_addr_counter) + 1);
ISIM gives me following warning, so my_addr_counter always remains to "xxxxxx"
 
at 5 ns(1), Instance /test_bram_mem/uut/Memory_In/U0/mem_module/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
---------------------------------------
ModelSim XE III/Starter
---------------------------------------
ModelSim is not going to find file xilinxcorelib.blk_mem_gen_v4_3.vhd, which is compatible to it.
 
# -- Compiling architecture my_memory_a of my_memory
# ** Error: (vcom-11) Could not find xilinxcorelib.blk_mem_gen_v4_3.
# ** Error: ipcore_dir/my_memory.vhd(66): (vcom-1195) Cannot find expanded name "xilinxcorelib.blk_mem_gen_v4_3".
---------------------------------------------------------------------------------------------------------
Can you suggest me any other way to check or where I can get the xilinxcorelib.blk_mem_gen_v4_3.vhd compatible for ModelSim XE III (I didn't find it on xilinx.com). Kindly give me guideline.

关于ISim问题，您如何看待初始化'my_addr_counter'？可能您不是，所以需要在信号声明中进行。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Regarding the ISim problem, how do you think are you initialising 'my_addr_counter'?
Probably you aren't, so need to do it in the signal declaration.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

是的，你是对的，我还没有初始化它，现在我只是在模拟（ISIM）中按顺序得到它。



以下为原文

Yes, you are correct, I have not initialized it, now I am getting it in sequence in simulation (ISIM) only.

嗨，
关于Modelsim XE III / Starter：
您是否为实际的ISE版本重新编译了Xilinx库（尤其是XilinxCorelib）？
有一个很好的模拟 
Eilert



以下为原文

Hi,
about Modelsim XE III/Starter:
Have you recompiled the Xilinx libraries (especially XilinxCorelib) for your actual ISE version?
 
Have a nice simulation
  Eilert
 
 
 

你好
之前我使用过Xilinx 9.2和我当时安装的ModelSim，同样使用12.3。



以下为原文

Hi
Earlier I was using Xilinx 9.2, and the ModelSim which I installed at that time, using the same for 12.3 also. 

嗨，
那么你一定要编译适用于Modelsim的ISE12.3附带的xilinx库。
您可以在其他目录中执行此操作，因此如有必要，您仍可以使用ISE 9.x的旧库。
有一个很好的综合 
Eilert



以下为原文

Hi,
then you should definitely compile the xilinx libraries that came with ISE12.3 for Modelsim.
You can do that in a different directory, so you can still use the old libs with ISE 9.x if necessary.
 
 
Have a nice synthesis
  Eilert