如何了解HDL和系统生成器生成代码

嗨莱恩。
我理解你的意图，但对于sysgen这个问题并没有多大意义。
（看一下sysgen代码，其中没有太多的行为内容。）
关键是sysgen（使用simulink原理图）基本上配置核心并在网表中实例化这些核心。
让我们忽略一下，程序员不能立即从头开始写下所有的coregen函数。
即使然后输入所有实例化端口列表也会浪费一个（希望收入很高的）专业HDL设计师。
同时以交互方式使用Coregen非常耗时。
从这个角度来看，sysgen只是提高了DSP设计的效率。
接下来是：与Matlab的连接允许进行非常强烈的测试和结果分析。
如果他能做的就是编写HDL Testbench，设计师如何处理这个？
他必须编写大量代码，只需几个matlab命令就可以做得更好。
当然，sysgen有其弱点。
这主要是当你需要做一些复杂的数据路径控制时。
但那怎么办？
主要是通过设计一些FSM然后保存在黑盒子块中或（对于非HDL人员）在MCode块中。
但是在这里我们回到了编辑器工具，所以如果你是一个普通的HDL设计师或使用sysgen，它就没有区别。
除了任何技术语言中某些人的“语法技巧”问题之外，更重要的一点是：设计师在理解和实施系统方面有多好。
你有没有读过一些论坛帖子？
如果他不知道FFT如何工作，采样频率对某些信号属性的影响是什么，以及......什么是UART以及如何使用它，那么专业HDL“程序员”有什么用呢？
对系统有深刻理解的人（DSP理论，计算机体系结构，数值计算），底层硬件（FPGA）和工具，仍然能够忽略这些多重主题，比仅仅是HDL“程序员”更有价值
只知道语法。
今天，除了HDL和数字设计技能之外，还需要更多。
想了解未来：看一下Xilinx Vivado软件。
关键词：以IP为中心等因为单个人不再能够通过编写HDL代码来填充实际的FPGA。
记住过去。
有多少工程师参与设计一个完全填充的19英寸机架（我的意思是大机器人，大约2米高）。现在用分立逻辑完成的工作只需一个芯片。虽然这些工具提高了生产率，但复杂的系统仍然存在
对球队的需求。孤独的英雄将在比赛中失利。
问候 
Eilert



以下为原文

Hi Ryan.
I understand your intent, but for sysgen this question does not really make sense.
(Take a look at sysgen code, there's not much behavioral stuff in it.)
 
The point is that sysgen (with the simulink schematics) basically configures cores and instantiates these in a netlist.
Let us ignore fo the moment, that a programmer can not write down all the coregen functions immediately from scratch.
Even then typing down all the instantiation port lists would be a waste for a (hopefully well paid) professional HDL designer.
Also working with Coregen interactively is very time consuming.
From this point of view sysgen just increases the productivity for DSP designs.
Then comes the next thing: The connectivity to Matlab allows for very intense testing and result analysis.
How would a designer deal with this if all he could do is to write a HDL Testbench?
He had to write tons of code that cold be done better with just a few matlab commands.
 
Of course sysgen has its weak points. That is mainly when you need to do some complex datapath controll.
But how's that done? Mostly by designing some FSM which then is hold in a Black box block or (for the non-HDL guys) in a MCode block. But here we are back to the editor tool, so it makes no difference if you are a plain HDL designer or using sysgen.
 
The more important point beyond the question of someones "syntactical skills" in any technical language is: How good is the designer in understanding and implementing a system.
Have you read acros some forum posts?
What good is  a professional HDL "programmer" if he doesn't know how a FFT works, what the impacts of the sampling frequency on some signal properties are and.... what a UART is and how to use it.
 
Someone who has a good understanding of the System (DSP theory, Computer architecture, numerical math), the underlying hardware (FPGA), and the tools and is still able to overlook these manyfold topics is more valuable than a mere HDL "programmer" who just knows syntax. Today there's more needed than just HDL and digital design skills.
 
Want to know about the future: Take a look at the Xilinx Vivado software. Keywords: IP-centric etc. because a single person is no longer able to fill actual FPGAs just by writing HDL code.
Remember the past. How many engineers were involved in designing a fully filled 19" rack (I mean the big ones, about 2m high) . What has been done then with discrete logic now goes in a single chip. While the tools have increased productivity the complex systems still demand for teams. Lonely heroes will lose in the competition.
 
Regards
  Eilert
 
 

eilert写道：
想了解未来：看一下Xilinx Vivado软件。
关键词：以IP为中心等因为单个人不再能够通过编写HDL代码来填充实际的FPGA。
这是一个荒谬的断言。
“单个人不再只是通过编写HDL代码就无法填充实际FPGA”的固有假设是，每个设计都将填充2,000,000个LUT FPGA，用于处理核心可用的各种标准化事物。
我的猜测是绝大多数FPGA都与我所做的一致 - 特殊数据处理和控制，没有IP核存在的东西，它们都适合于较小或中等的斯巴达之一
3或6个器件，或者可能是最小的Virtex器件，因为需要最新的ADC上的高速串行I / O.
是否真的存在将ARM嵌入FPGA的巨大市场？
人们正在做什么，这是通过将（便宜得多的）独立ARM或PPC芯片放在一个（便宜得多的）小型FPGA旁边而无法实现的？
当然，奖金与单独的部分是我们没有被工具或核心搞砸，任何使用EDK的人都知道我在说什么。
（我认识一个正在为天文台工作的人，在超级大型FPGA中进行大量的FFT，但它是一次性仪器，所以数量几乎是一位数，处理控制的处理器不在
FPGA。）
----------------------------是的，我这样做是为了谋生。



以下为原文

eilert wrote:
 
Want to know about the future: Take a look at the Xilinx Vivado software. Keywords: IP-centric etc. because a single person is no longer able to fill actual FPGAs just by writing HDL code.
  

That's an absurd assertion. 
 
The assumption inherent in that "a single person is no longer able to fill actual FPGAs just by writing HDL code" is that every design will be the sort that fills a 2,000,000 LUT FPGA doing all sorts of standardized things for which cores are available.
 
My guess is that the great majority of FPGAs are along the lines of what I do -- special-sauce data handling and control, the kind of stuff for which no IP cores exist, and it all fits into one of the smaller or moderate Spartan 3 or 6 devices, or perhaps the smallest Virtex device because of the need for high-speed serial I/O that's on the newest ADCs.
 
Is there really that big a market for embedding an ARM into an FPGA? What are people doing with that, which can't be accomplished by putting a (much cheaper) standalone ARM or PPC chip next to a (much cheaper) smaller FPGA? The bonus, of course, with the separate parts is that we're not screwed by the tools or the cores, and anyone who's used the EDK knows what I'm talking about. 
 
(I know a guy who's doing work for an observatory, doing lots of FFTs in a super-duper-big FPGA, but it's a one-off instrument so the quantity is pretty much single digit, and the processor handling the control is not in the FPGA.)
----------------------------Yes, I do this for a living.

嗨巴斯曼，
同意，“实际FPGA”一词的选择过于粗心。
对不起。
当然，我指的是大型设备以及设备尺寸在过去几年中的增长情况。
（如果写了一些很长的答案，但论坛系统破坏了它。:-(
当写一篇文章需要更长时间时会发生这种情况。）
正如你在上一篇文章中所看到的那样，我在谈论的系统充满了大型的19“机架，所以它与你所做的与所提到的机架内的一个或多个PCB相比的东西不同，能够容纳一些多层PCB或更多
（我的意思是DSP /微处理器时代的机架，而不仅仅是普通的MSI逻辑设备）
亲切的问候 
Eilert



以下为原文

Hi Bassman,
agreed, the term "actual FPGAs" was choosen too carelessly. Sorry for that.
Of course I refered to the big ones and how the device sizes grew within the last years.
 
(If written some long answer, but the forum system busted it. :-(
 That happens when writing a post takes a little longer.)
 
As you could see in my last post I was talking about systems that filled up large 19" racks, so it's different from the stuff you do which would compare to one or more PCBs inside the mentioned rack, capable of holding some dozend PCBs or more. (And I mean racks of the DSP/Microprocessor era, not just plain MSI logic devices)
 
Kind regards
  Eilert
 

System Generator只不过是使用原语和coregen核心的原理图输入。
确定你也可以做一些有限的M文件的东西（这比连接整个地方的电线，imho更好）。
它是Viewdraw前V2部件中的Logic Blocks。
我使用VHDL开始了FPGA世界之旅。
必须使用Simulink / SysGen是缓慢而繁琐的，并且充满了“核心”，我不喜欢在我的设计中使用它，除非我必须（FIFO等）。
当我尝试添加块盒组件时，该工具就会冻结，所以我甚至无法尝试将“真正的”VHDL与现有的simulink设计集成。
更不用说像这些强制供应商锁定的工具，如果你不得不移植供应商，则需要进行全面的重新设计。
缺少一些令人敬畏的（V）HDL语言功能，可以使代码易于重用，紧凑，可读和便携。
并且模型不是非常SCM工具（CVS，SVN，Hg等）友好并且使版本控制变得困难或不可能。
没有直接比较设计的两个版本的方法。
在（V）HDL（通常与系统工程师/架构师合作）中设计/维护整个系统（多个板）没有任何问题。
当然，并不是evey数字设计师也是一名系统工程师，但很多人戴上这顶帽子并且穿得很好。
你也没有“编程”HDL，你用它来设计/描述一个架构。
这些工具吐出结构HDL或二进制网表，但没有任何可读性。
另一方面，它是系统工程师（与纯matlab相对）在与硬件工程师合作时使用的一个很好的原型设计工具。
首先在矢量精度/位宽上着色的能力也很好（但是在失去控制的情况下）。
我看到这个工具的最佳位置是验证。
如果传统的仿真可以与matlab / simulink环境集成，那么可以提高验证的质量和程度，减少设计迭代次数和漏洞数量，并在真实硬件中的现场找到。
相同（或非常相似）的验证环境可用于系统设计，HDL仿真和真实硬件。
走开盒子。



以下为原文

System Generator is nothing more than schematic entry using primitives and coregen cores.  sure you can also do some limited M-file stuff too (and that's better than connecting wires all over the place, imho).  
 
its a throw back to Logic Blocks in Viewdraw pre-V2 parts.
 
I started my journey in the world of FPGAs using VHDL.  Having to use Simulink/SysGen is slow and cumbersome and full of "cores", which I dislike using in my designs unless I must (FIFOs, etc).  The tool just freezes when I try to add the block box component, so I can't even try and integrate "real" VHDL with an existing simulink design.
 
not to mention tools like these force vendor lock in and a total redesign is necessary if you had to port vendors.
 
and missing are some awesome (V)HDL language features that can make code easily reusable, compact, readable and portable.
 
and a model is not very SCM tool (CVS, SVN, Hg, etc, etc) friendly and make version control difficult or impossible.  no direct way to compare two versions of a design either.
 
I have NO problems designing/maintaining entire systems (multiple boards) in (V)HDL (usually working with system engineer/architect).  Sure, not evey digital designer is also a system engineer, but many do wear that hat and wear it well.
 
you also don't "program" HDL, you design/describe an architecture with it.   these tools spit out structural HDL or binary netlists, but nothing readable.
 
on the flip side, it is a good prototyping tool for a system engineer (as opposed to pure matlab) to use when working with a hardware engineer.  the ability to gloss over vector precision/bit widths at first is nice too (but at the loss of control).
 
the best place I see this tool is in verification.  If a traditional simulation could be integrated with the matlab/simulink environment, maybe the quality and degree of verification could be improved and reduce design iterations and number of bugs that slip through and are found in the field in real HW.  the same (or very similar) verification environment could be used for system design, HDL simulation and real HW.
 
stepping off the box.

嗨，艾勒特，谢谢你回答我的问题。
我理解你的手段，它有所帮助。
最好，瑞安



以下为原文

Hi Eilert,

Thanks for answering my question. I understand your means and it helps.

Best,

Ryan

“当我尝试添加块盒组件时，该工具就会冻结，所以我甚至无法尝试将”真正的“VHDL与现有的simulink设计集成。”这是什么意思？
虽然它必须遵守一些设计规则，但我认为黑盒子是可行的。“缺少一些令人敬畏的（V）HDL语言功能，可以使代码易于重复使用，紧凑，可读和便携。”你能给我一个小例子吗？
？
可能我不是一个经验丰富的硬件架构设计师。
我不太了解VHDL太棒的功能.Best，Ryan



以下为原文

"The tool just freezes when I try to add the block box component, so I can't even try and integrate "real" VHDL with an existing simulink design."

What do you mean by this?  the black box works I think, although it has to obey some design rules.

"missing are some awesome (V)HDL language features that can make code easily reusable, compact, readable and portable."

Could you give me a small example fo this?  Probably I'm not a experienced hardware architecture designer. i don't know too much VHDL awesome features.

Best,

Ryan