SAR6采样时钟如何工作

你好，
我的项目consistsinprogramming PSoC作为信号adquisitor利用ADCs不同类型才能看到它们之间的差异。
现在我尝试用sar6 ADC但我不了解它是如何工作的时候得到的样品。
当我阅读数据表和API函数我知道样品的当我叫sar6_cgetsample()，它用一些微秒转换示例。那么，如何影响模拟列时钟采样率？看来，采样率将是我的sar6_cgetsample()函数代替模拟柱时钟的相关代码。
另一个疑问是为什么数据表表说，转换时间为20微秒，与CPU 12 MHz和250千赫fclock条件，若数据表说，这个时间是周期的采样时钟的六倍。它是不是可变的参数？
最后，了解fclockmentioned的datasheet inthetables作为采样时钟相同（Φ和Φ），为什么是限制为333千赫如果它取决于模拟列钟吗？它会是几兆赫，不是吗？
我误解了什么？
谢谢您，



     以下为原文
  Hello,
    My project consists in programming the PSoC as a signal adquisitor using the different types of ADCs in order to see the differences between them.
    Now I am trying to use the SAR6 ADC but I don't fully understand how it works when it get the samples.
    When I read the datasheet and the API functions I understand that the sample is taken when I call the SAR6_cGetSample(), and it takes some microseconds to convert the sample. Then, how does the Analog Column Clock influence in the Sample Rate? It seems that the Sample Rate would be related to the code where I have the SAR6_cGetSample() function instead of the Analog Column Clock.
    Another doubt is why some tables of the datasheet say that the Conversion Time is 20 microseconds with the condition of a CPU of 12 MHz and fclock of 250 kHz, if then the datasheet says that this time is six times the period of the sample clock. Is it a variable parameter or not?
    And finally, understanding that fclock mentioned in the tables of the datasheet is the same as sample clock (phi1 and phi2), why is it limited to 333 kHz if it depends on the Analog Column Clock? It would be some MHz, couldn't it?
    What I am misunderstanding?
    Thank you,