FMC连接器引脚没有任何输入信号也能看到某些位配置

对不起，我在帖子中犯了一个错误。
这是正确的版本：
“另一个问题是，当我加载固定位配置时，我设法读取它，但如果配置发生变化（随着时间的推移），输出上的某些位是错误的。你有什么建议吗？”



以下为原文

Sorry I made a mistake in the post. That's the correct version:
 
"Another problem is that when I load a fixed bit configuration I manage to read it, but if the configuration changes (in the course of time) some bits are wrong on the output. Have you any suggestion?"

你在问为什么FPGA配置会改变吗？
或者你在问为什么两种配置表现出不同的行为？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

Are you asking why the FPGA configuration changes?
Or are you asking why two configurations exhibit different behaviour?
 
-- Bob Elkind
SIGNATURE:
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Summary:
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也许我没有添加足够的细节，抱歉。
我的目标是使用ML605评估板的fmc（HPC）连接器检查数据的正确加载。
我正在使用具有8个差分位的外部模式发生器作为输入信号。
使用的时钟信号来自200 MHz ML605板内部振荡器。
实现的VHDL代码仅从模式生成器获取输入数据并将其存储到寄存器中，该寄存器的值由chipscope可视化。
问题：
1.在几十MHz的频率范围内，一个（有时两个）差分比特开始出现奇怪的行为。
它不遵循输入信号。
2.即使没有源连接到FMC连接器，它也不会将0值存储到寄存器中。
（我附上了chipcope截图）
考虑：
我尝试在使用过的FMC引脚上设置下拉和上拉配置（没有结果）
我在VHDL代码中将寄存器的初始值设置为0。
我使用一个清除开关来重置寄存器值，但即使在重置命令后我也有问题。
考虑到我使用差分信号，我觉得它可能是噪音。
你觉得怎么样？
提前致谢



以下为原文

Maybe I didn't add enough details, sorry.
 
My target is to check the correct loading of data using the fmc (HPC) connector of ML605 evaluation board.
 
I'm using, as input signals, an external pattern generator with 8 differential bits.
The used clock signal comes from the 200 MHz ML605 board internal oscillator.
 
The implemented VHDL code just takes the input data from pattern generator and stores it into a register whose value is visualized by chipscope.
 
Problems:
 
1. Within a frequency range of tens of MHz, one (sometimes two) of the differential bits starts to have a strange behavior. It doesn't follow the input signal.
 
2. Even if no source is connected to FMC connector it doesn't store 0 value into the register. (I attached the chipscope screenshot)
 
Consideration:
 
I tried to set both pulldown and pullup configuration on the used FMC pins (with no results)
I set the initial value of register to 0 in the VHDL code.
I use a clear switch to reset the register value, but even after the reset command I have the problem.
Considering that I'm using differential signals it sounds strange to me it could be noise.
 
What do you think about that?
 
Thanks in advance
 

调试此问题有很多不同的地方。
这是一个建议：
对模式生成器进行编程以输出所有“0”的模式，然后输出所有“1”。
将模式发生器输出编程为在“0”和“1”之间切换的单个位。
重复所有位，一次只切换一个位。
这是传统的短裤/开场测试，或多或少。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
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以下为原文

There are many different places to start with debugging this problem.  Here is one suggestion:
 

• Program the pattern generator to output patterns of all '0s', and then all '1s'.
  
• Program the pattern generator output a single bit toggling between '0' and '1'.  Repeat for all bits, toggling only one at a time.
  

This is a traditional shorts/opens test, more or less.
 
-- Bob Elkind
SIGNATURE:
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2. Search the forums (and search the web) for similar topics.
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如果LVDS缓冲器未连接，差分终端电阻将把P和N两个输入拉到相同的电压。
由于P / N差分电压不会大于所需的最小Vidiff规范，因此IBUFDS的输出将不是确定性的。
在使用模式生成器的情况下，可能的原因是您没有满足输入建立/保持值，并且数据正在跨边界注册，偶尔会导致亚稳态事件。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

If an LVDS buffer is unconnected the differential termination resistor will pull both of the P and N inputs to same voltage.  Since the P/N differential voltage will not be greater than the required minimum Vidiff specifcation the output of the IBUFDS will not be deterministic.
 
In the case of using the pattern generator, the likely cause is that you are not meeting the input setup/hold values and the data is being registered across boundaries and occasionally resulting in metastable events.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

在使用模式生成器的情况下，可能的原因是您没有满足输入建立/保持值，并且数据正在跨边界注册，偶尔会导致亚稳态事件。
嗯...这可以解释随着模式发生器更新速率与固定（200MHz）采样频率的增加而增加的“失败”发生率。
但奇怪的是，芯片内窥镜中只有一个数据位似乎正在摆脱。
也许说明中仍然缺少有用的细节。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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以下为原文

In the case of using the pattern generator, the likely cause is that you are not meeting the input setup/hold values and the data is being registered across boundaries and occasionally resulting in metastable events.
 
Hmmm...  This might explain the increased "failure" incidence with increased pattern generator update rate vs. the fixed (200MHz) sampling frequency.  Odd that only one data bit in the chipscope trace seems to be wigging out, though.
 
Perhaps there are useful details still missing from the description.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我试图把“00000000”和“11111111”序列放在一起工作（输入固定）。
相反，当我输入“01010101”序列时，我的输出不稳定。
即使没有输入apllied我有一些奇怪的行为。
模式发生器是“Agilent 16720A 300 M矢量/ s模式发生器”。
数据线提供ECL端接（470欧姆;至-3.25V）差分信号。
有一个特定的pod（我目前没有）将ECL信号转换为LVDS信号，（我不知道这是否是主要问题）。
非常感谢



以下为原文

I tried to put "00000000" and "11111111" sequences and it works (input fixed). Instead when I put "01010101" sequence I have an unstable output.
Even with no input apllied I have some strange behaviour.
 
The pattern generator is "Agilent 16720A 300 M Vectors/s Pattern Generator". The data cables provide an ECL-terminated (470 ohm; to -3.25V) differential signal. There is a specific pod (that I don't have at the moment) to convert the ECL signal intto LVDS signal, (I don't know if this is the main problem).
 
thanks a lot

报告测试失败或异常时，必须包含所有有用的详细信息。
固定输入模式或移位输入模式
如果改变输入模式，模式改变频率是多少
什么位不正确 - 请包括预期结果与实际结果
故障是与所有位和输入模式以及更新频率一致的，或者故障发生率是否变化
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

When reporting a test failure or anomaly, it is essential that you include all useful details.
 

• fixed input pattern, or shifting input pattern
  
• if shifting input patterns, what is the pattern change frequency
  
• what bits are incorrect -- please include expected results vs. actual results
  
• is the failuir consistent with all bits and input patterns and update frequencies, or does the failure incidence vary
  

 
Does this make sense?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

输入模式“00000000”==>输出模式“00000000”（没关系）
输入模式“111111111”==>输出模式“111111111”（没关系）
输入模式“01010101”==>输出模式不稳定（随机时间位变化，不遵循输入模式） 
我认为外部位是问题更多的问题
没有输入模式==>随机输出模式（参见上面的附图）问题



以下为原文

input pattern "00000000"     ==>     output pattern "00000000"   (that's ok)
input pattern "111111111"     ==>     output pattern "111111111"   (that's ok)
 
input pattern "01010101"     ==>     output pattern not stable (bit change in time at random and don't follow the input patter) 
                                                              I nocticed that the external bit are the more problematic  PROBLEM
no iput pattern                        ==>     random output pattern (see the figure I attached above)  PROBLEM

我重复在这个帖子中＃5和＃6帖子中提出的建议。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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我没有支付论坛帖子的费用。
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以下为原文

I repeat the suggestions made in post #5 and #6 in this thread.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

>数据线提供ECL端接（470欧姆;至-3.25V）差分信号。
这些信号的实际输出摆幅是多少？
您可能违反了Virtex-6器件的最大Vin。
你应该追捕那个ECL-to-LVDS pod。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> The data cables provide an ECL-terminated (470 ohm; to -3.25V) differential signal.
 
What is the actually output swing of these signals?  You may be violating the maximum Vin of the Virtex-6 device.  You should hunt down that ECL-to-LVDS pod.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com