怎么从Virtex-4过渡到Serie-7

请注意，但是：MicroBlaze在Virtex-7中的运行速度是否比Virtex-4快得多？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Apologies for butting in, but:
Will a MicroBlaze run much faster in a Virtex-7 than a Virtex-4?

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"If it don't work in simulation, it won't work on the board."

“许多”？
好吧，我不会那么远。
它可能会比V4的运行速度提高1.5倍，但请记住，405PPC可以在V4中以400 MHz运行（PLB总线为100 MHz）。
无论如何，Zynq A9以800 MHz运行可能是一个更好的选择，全方位。
这取决于他在FPGA设计中需要多少空间。
我会看看70405设备。
奥斯汀
Austin Lesea主要工程师Xilinx San Jose



以下为原文

"Much"?
 
Well, I wouldn't go that far.  Perhaps it will go 1.5X what it ran at in V4, but remember the 405PPC could run at 400 MHz in V4 (with the PLB bus at 100 MHz).
 
In any event, the Zynq A9's running at 800 MHz might be a better choice, all-around.  It depends on how much space he needs in the FPGA part of his design.  I would look at the 70405device.

Austin
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

你好奥斯汀，
实际上，我使用100MHz的PPC，它主要用于管理我的数据流。
目前处理速度不是问题。
我更关心的是我需要的I / O数量。
我实际上有133xHZ的4x或5x 8MB ZBT RAM，我几乎要同时访问（我从3或4 ZBT读取并写入1 ZBT）。
我正在寻找是否可以使用一个DDR2或DDR3来取代ZBT RAM。
你相信这是可以实现的吗？
PS。
在与ZBT同时读写时，PPC不参与。
感谢您的支持。



以下为原文

Hello Austin,
 
Actually, I use the PPC at 100MHz and it is used mainly to manage my dataflow.  The speed of the processing is not an issue for now.  My concern is more with the number of I/O I need.  I actually have 4x or 5x 8MB ZBT RAM at 133MHZ that I have to access almost simultaneously (I read from 3 or 4 ZBT and write in 1 ZBT).  I'm looking if I can use one DDR2 or DDR3 to replace the ZBT RAMs.  Do you believe that it is acheivable?
 
PS.  The PPC is not involved when reading and writing to simultaneously to the ZBTs. 
 
Thanks for your support.

T，
查阅数据表，了解哪些封装/部件有足够的IO引脚。
然后，我会使用该设计来定位该设备，并查看它是否适合该部分，最后，我会看看它是否能够满足时序要求。
我认为没有理由不这样做：你只需要指定正确的部分。
你现在用什么部分？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

t,
 
Consult the datasheet to see what package/part has enough IO pins.  Then, I would target that device with the design, and see if it fits in that part, and finally, I would see if it can meet timing.
 
I see no reason why this can't be done:  you just need to specify the right part.

What part do you usew now?
Austin Lesea
Principal Engineer
Xilinx San Jose

实际上，我正在使用Virtex4 FX100。
对于5个ZBT，我至少需要大约300个I / O.
为了节省I / O并使用Zynq，我可以将ZBT ram更改为DDR2或DDR3，但我想知道我是否能够以133MHz的“有效速率”读取和写入5个不同的存储区。
对于133MHz的每个输入数据，我有4个读操作和1个写操作。
你觉得有可能吗？
谢谢



以下为原文

Actually, I'm using the Virtex4 FX100.  For 5 ZBTs, i need at least around 300 I/Os.
 
To save I/Os and use the Zynq, I could change the ZBT ram to DDR2 or DDR3 but I wonder if  I will be able to read and write to five differents memory zones at a "effective rate" of 133MHz.  For each input data at 133MHz, I have 4 read operations and 1 write operation.
 
Do you think it is possible?
 
Thanks

T，
好吧，不，我认为Zynq太小了，尽管已经为ARM处理器内置了一个内存接口。
但是，如果考虑到硬化的东西，以及ARM的内置存储器接口（并在那里放置大量内存），它可能只是工作....与V4相比，它确实有6LUT和两个DFF
4LUT +每个逻辑单元只有一个DFF。
因此，具有足够IO的Kintex 7部分可能是最佳选择。
xc7k325t的LUT计数可能是3倍，不考虑6LUT，因此可能更像逻辑的4.5倍。
除此之外，你在CLB中获得两倍的DFF，因此它是V4部分的DFF的~9倍。
这对于MicroBlaze来说是很大的空间，并且在此设备中使用额外的BRAM，您可以使用MicroBlaze的数据和指令缓存。
大量的内存控制器结构，现在只需要足够的IO引脚。
有500个IO，因此取决于封装（676或900引脚）以及HR与HP IO引脚的混合（HP性能更高，1.8v限制，主要用于非常快的存储器 -  HP高达3.3
v IO，以及稍慢的IO但也可以用于更低的电压），其中一个设备应该可以完成这项工作。
如果325太大，676封装有相同的引脚，你可以去一个较小的设备160.如果325太小，你可以去410，也在同一个包（up，
或者在没有重新布局的情况下，在http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf第3页的每个表的Kintex相同的包中。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

t,
 
OK, no, I think the Zynq would be too small, in spite of having one memeory interface already built in for the ARM processors.  But, if you take the hardened stuff into account, and the built in memory interface for the ARM (and put a lot of memory out there), it might just work....it does have 6LUT and two DFF as compared to V4's 4LUT + just one DFF per logic cell.

So, a Kintex 7 part, with enough IO, is probably the best choice.  The xc7k325t has perhaps 3X the LUT count, not taking into account the 6LUT, so that is probably more like 4.5X as much logic.  Along with that, you get twice as many DFF in the CLB, so that is ~9X the DFF of the V4 part.  That is a lot of room for MicroBlaze, and with the extra BRAM in this device, you may use the data and instruction caches for MicroBlaze.  Lots of fabric for memory controllers, now all you need are enough IO pins.  There are 500 IO, so depending on the package (676 or 900 pins) and mix of HR vs HP IO pins (HP are higher performance, 1.8v limited, which get used mostly for very fast memories--HP are the up  to 3.3v IO, and a bit slower IO but can be used for lower voltages too), one of these devices should do the job.
 
If the 325 is too big, the 676 package has the same pins, and you can go down to a smaller device, the 160.  If the 325 is too small, you can go to the 410, also in the same package (up, or down, without relayout, in Kintex same package per tables in     http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf  page 3).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

嗨，我是virtex 5系列的初学者并且正在努力学习。
据我所知，在下载比特流后，virtex 5 FPGA开始出现。
但在此处理之前，处理配置序列如上电 - >清除配置存储器 - >采样模式引脚等。
有没有其他处理器来处理这个状态机？
有限状态机中的状态信号是什么？
正如我们所说，无论模式引脚M2，M1，M0如何，JTAG始终可用。
如果选择任何其他mose，可以是TDI，TDO，TMS＆amp;的状态。
TCK（JTAG信号）。
任何对相关事情的评论将不胜感激。
谢谢



以下为原文

Hi I am a beginner at virtex 5 series and trying to study. As far as i know the virtex 5 FPGA comes into picture after we download the bitstream. But before this proces who handles the configuration sequence like power-up->clear config memory-> sample mode pins etc.
Is there any othe processor which handles this state machine?
what can be the status signals during the Finite state machine?
 
As we say that irrespective of the mode pins M2,M1,M0, the JTAG is always available. In case if any other mose is selected what can be the status of TDI,TDO,TMS & TCK (JTAG signals).
 
Any comment to the related things will be appreciated.
Thank  you

K，
请不要在旧线程中启动新主题。
在适当的论坛中发布您的问题（如新用户）。
并且，在发布此问题之前，您可能需要考虑阅读配置用户指南....
Austin Lesea主要工程师Xilinx San Jose



以下为原文

k,
 
Please do not start a new topic in an old thread.
Post your question in the appropriate forum (like new users).
 
And, before you post this question, you might want to consider reading the configuration user's guide....
Austin Lesea
Principal Engineer
Xilinx San Jose