[问答]

如何让一个从路由织物平行于ALU输入

1388 Verilog

问答对人有帮助，内容完整，我也想知道答案 0 你好，我正在尝试学习DATAPATH、Verilog和配置工具。我不能找出如何让一个从路由织物平行于ALU输入。根据PSoC 5 TRM，图23-6（节）和图23-25（P170）有一种源的输入到ALU的并行输入路由。我已经启用CFB EN在cfgram，然后选用PI SEL引脚（登记cfg15-14）。我做不出ISI从来没有看到PI在下拉在cfgram段SRCA。我必须手动更改Verilog文件吗？我没能猜到的价值是什么（例如` cs_srca_a0显然是A0）。提前感谢。以上来自于百度翻译以下为原文 Hi, I am trying to learn the datapath, verilog and the configuration tool. I can't work out how to get an input to the ALU from the parrallel in routed fabric. According to the PSoC 5 TRM, fig 23-6 (p.154) and fig 23-25 (p170) there is a way to source the A input to the ALU from the parallel input routing. I've enabled CFB EN in the CFGRAM, and then selected PI SEL to PIN (register CFG15-14). What I can't work out is I never see PI in the drop down for SRCA in the CFGRAM section. Do I have to manually change it in the verilog file? I have not been able to guess what the value is (e.g. `CS_SRCA_A0 is obviously A0). Thanks in advance. 0
2019-2-12 11:44:10　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 36切53 该类别下有 65 个回答。邀请回答 hnui2002 该类别下有 50 个回答。邀请回答细水爱长流该类别下有 33 个回答。邀请回答不cdvdhgdh 该类别下有 31 个回答。邀请回答 iwuwjgj 该类别下有 26 个回答。邀请回答 cslb2000 该类别下有 25 个回答。邀请回答 ggfx 该类别下有 23 个回答。邀请回答珠海易胜该类别下有 23 个回答。邀请回答 h1654155958.0210 该类别下有 22 个回答。邀请回答 hrtuoyu 该类别下有 22 个回答。邀请回答 ncmza 该类别下有 21 个回答。邀请回答 shaoye88 该类别下有 21 个回答。邀请回答瑾年Invader 该类别下有 20 个回答。邀请回答望望Ll 该类别下有 20 个回答。邀请回答 april_yu 该类别下有 20 个回答。邀请回答 zkzk196599 该类别下有 19 个回答。邀请回答 nvwuwy 该类别下有 18 个回答。邀请回答 lucas_songlea 该类别下有 18 个回答。邀请回答 fan7572 该类别下有 17 个回答。邀请回答 zhan81411 该类别下有 17 个回答。邀请回答举报莫循虎相关推荐 • 小弟初学VHDL,看别人的结构写了个ALU的程序，但编译不过... 2763 • 4G路由器在选择时可以从三个要点入手 1315 • STM32的ALU检测有必要吗 2036 • 请问单片机的ALU、ACC功能是什么？ 364 • 怎么在ALU UDB项目中使用DMA？ 1087 • 在i.MX RT1170上是否可以从PCS gpio路由输出到另一个引脚？ 319 • ALU算数运算为什么没有直接传2个立即数的? 1069 • 请问怎么设计一种边缘耦合的平行耦合线带通滤波器？ 2060 • 求大神指导，最近想用labview弄一个能登录和管理路由器的软件 4214 • 8位alu设计 2773 11个回答

答案对人有帮助，有参考价值 0 你好，对ALUCN的SRCA输入来自累加器寄存器或从路由结构中并行输入。在数据路径工具中CFRAM部分的8个配置选择中，每个SRCA下拉都可以使用累加器选择。并行（in）（PI）可以被选择为静态或动态的输入（PSoC5 TRM FIG 23-25，PG 170）。静态操作涉及将PI SELIT设置为数据路径配置工具中的PIN（CFG15—14）。这迫使ALUASRC在数据路径工具的CFRAM部分中对所有8种配置都是PI。动态操作涉及CFCFM段中的CFB EN位，并在数据路径工具的CFG15—14中启用PI DYNIT。CFB EN位设置在CFGRAMsection上可用的8种配置中的每一种上。注意，如果在选择中使用并行的PI-SEL或PI-DYN（具有CFBN位集），则CFRM部分中的SRCA输入下拉选择将不影响SRCCANPUT。您可以通过查看由数据路径配置工具生成的Verilog文件来验证选择。例如，Verilog文件将通过下面的行指示累加器或PI选择累加器选择——“SCYA0SRCYACC” PISSION——“SCA0A0SRCPIN” ——Sathya 以上来自于百度翻译以下为原文 Hello, SRCA input to the ALU can come from either accumulator registers or Parallel In from routing fabric. The Accumulator selections are available in the SRCA dropdown for each of the 8 configuration selection of CFGRAM section in the Datapath tool. The Parallel In (PI) can be selected as input to ALU either statically or dynamically (PSoC 5 TRM Fig 23-25, pg 170). The static operation involves setting the PI SEL bit to PIN (CFG15-14) in the Datapath configuration tool. This forces the ALU ASRC to be PI for all 8 configurations in the CFGRAM section of the datapath tool. The dynamic operation involves enabling the CFB EN bit in the CFGRAM section and enabling PI DYN bit in CFG15-14 of the datapath tool. The CFB EN bit is set on each of the 8 configurations available in CFGRAM section. Note the SRCA input drop down selection in the CFGRAM section will have no bearing on the SRCA input if PI SEL or PI DYN (with CFB EN bit set) is enabled to use Parallel In selection. You can verify the selections by looking at the verilog file generated by the Datapath Configuration tool. For example, the verilog file will indicate an Accumulator or PI selection by the following line - Accumulator Selection - `SC_A0_SRC_ACC PI Selection -`SC_A0_SRC_PIN --Sathya

2019-2-12 11:58:19 评论举报王建华

答案对人有帮助，有参考价值 0 请注意，PSoC 5不支持动态并行输入操作。萨蒂亚以上来自于百度翻译以下为原文 Please note that the dynamic Parallel Input operation is not supported with PSoC 5. Sathya

2019-2-12 12:12:49 评论举报王建华

答案对人有帮助，有参考价值 0 请注意，动态并行输入操作不支持PSoC 5。萨蒂亚谢谢你的回答。澄清： PSoC 5这是不可能使用PI动态运行在TRM表示？因此，为了使用并行输入我必须选择循环流化床EN位所有配置的cfgram？以上来自于百度翻译以下为原文 Please note that the dynamic Parallel Input operation is not supported with PSoC 5. Sathya Thanks for your answers. to clarify: for PSoC 5 it is not possible to use the PI dynamic operation as indicated in the TRM? therefore, in order to use parallel input do I have to select the CFB EN bit in all 8 configurations for the CFGRAM?

2019-2-12 12:29:55 评论举报莫循虎

SATH发布于24八月2012日下午1:40下午PSP柏树员工4论坛帖子请注意，动态并行输入操作不支持PSoC 5。
萨蒂亚
你从哪里得到这些信息？这对我来说真的很傻

以上来自于百度翻译

以下为原文

	sath posted on 24 Aug 2012 01:40 PM PST Cypress Employee 4 Forum Posts

    Please note that the dynamic Parallel Input operation is not supported with PSoC 5.
    Sathya

    where do you have this information from? This would be really silly for me

2019-2-12 12:47:19 评论

李玉英

答案对人有帮助，有参考价值 0 PI是否支持在PSoC5LP中？鲍勃以上来自于百度翻译以下为原文 Is the PI supported in PSoC5LP ? Bob

2019-2-12 13:03:01 评论举报王琳

答案对人有帮助，有参考价值 0 PSOC 3的工程样机和生产PSoC 5设备具有原来的UDB体系结构，在并行处理中使用有限。如果你使用这些芯片并联，然后有一点，你可以做自个输入到ALU总是在信号并行。这被理解为限制为PSoC 5lp udb进行了更新，使并联在一个动态切换功能的PSoC 3和生产版本。其他重要的新功能加入udb PSoC 3 / 5lp版本能力设置FIFO，可以读写由udb。这可以提供一些需要的存储的一些应用。以前一边一个FIFO必须连接到UDB和CPU的另一面。萨蒂亚以上来自于百度翻译以下为原文 The engineering samples of PSoC 3 and the production PSoC 5 devices had the original UDB architecture and it had limited usage for parallel in. In these chips if you used parallel in, then there was little that you could do since the A input to the ALU would always be the Parallel In signal. This was understood as a limitation and for the production version of PSoC 3 and for PSoC 5LP the UDB was updated to make Parallel In a dynamically switchable feature. The other significant new feature added with the PSoC 3 / 5LP version of the UDB is the ability to set a FIFO up so that it can be both read and written by the UDB. This can provide some much needed storage for some applications. Previously one side of a FIFO must be connected to the UDB and the other side to the CPU. Sathya

2019-2-12 13:17:58 评论举报王建华

答案对人有帮助，有参考价值 0 谢谢，Sathya！鲍勃以上来自于百度翻译以下为原文 Thx, Sathya! Bob

2019-2-12 13:35:03 评论举报王琳

答案对人有帮助，有参考价值 0 需要一个证明，那psoc5不同于psoc5lp说到通路并行：TRM为家庭显示数据通路的部分是相同的。以上来自于百度翻译以下为原文 need a proof, that psoc5 is different from psoc5lp when it comes to datapath parallel in: TRM for both families shows that datapath part is identical.

2019-2-12 13:47:43 评论举报关睿

答案对人有帮助，有参考价值 0 你在问什么？我想我在这里看到了一些信息，暗示了ppi在PSoC5上被破坏了。我从PSoC5LP开始加入PSoC世界。我可以验证它是否有效。我们使用它为一个8位并行总线使用DMA高速处理器间通信对一些分布式处理器设计在我们的几个产品。你需要看一个工作Verilog吗？预计起飞时间以上来自于百度翻译以下为原文 what are you asking? I think I saw some info on here that said/implied that the PI was broken/unusable on the psoc5. I joined the psoc world starting with the psoc5lp. I can verify that it works on it. We use it for an 8bit parallel bus using dma for high speed interprocessor communication on some distributed processor designs in several of our products. Do you need to see a working verilog? Ed

2019-2-12 13:59:40 评论举报胡卫伟

答案对人有帮助，有参考价值 0 有没有勘误表？我找不到任何东西。以上来自于百度翻译以下为原文 is there any errata sheet? I could not find any.

2019-2-12 14:08:15 评论举报关睿

答案对人有帮助，有参考价值 0 如果有人感兴趣的话，根据“平方根计算”，PSoC5和PSoC5LP之间的区别是寄存器FIFO。它不工作或存在于PSoC5中。以上来自于百度翻译以下为原文 well, if it's interesting to somebody -- according to "square root computation", the difference between psoc5 and psoc5lp is registers fifo. it doesn't work or exist in psoc5.

2019-2-12 14:16:37 评论举报关睿