小弟初学VHDL,看别人的结构写了个ALU的程序，但编译不过...

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LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE IEEE.std_logic_unsigned.ALL;

USE IEEE.std_logic_arith.ALL;

entity ALU is

port(cin: in std_logic;

alu_function: in std_logic_vector(2 downto 0);

a_in: in std_logic_vector(7 downto 0);

b_in: in std_logic_vector(7 downto 0);

alu_out: out std_logic_vector(7 downto 0);

z: out std_logic;

c: out std_logic;

v: out std_logic;

                s: out std_logic

);

end ALU;

Architecture win of ALU is

signal midout: std_logic_vector(15 downto 0);

signal temp: std_logic_vector(15 downto 0);

begin

process(a_in,b_in,alu_function)

constant ADD:std_logic_vector:="000";

constant SUB:std_logic_vector:="001";

constant ANDOP:std_logic_vector:="010";

constant OROP:std_logic_vector:="011";

constant XOROP:std_logic_vector:="100";

constant SHL:std_logic_vector:="101";

constant SHR:std_logic_vector:="110";

cinextend:="000000000000000"&cin;

begin

case alu_function is

when ADD=>midout<=a_in + b_in + cin;

when SUB=>midout<=b_in - a_in;

when ANDOP=>midout<=a_in and b_in;

when OROP=>midout<=a_in or b_in;

when XOROP=>midout<=a_in xor b_in;

when SHL=>midout<=b_in(14 downto 0)&"0";

when SHR=>midout<="0"&b_in(15 downto 0);

when others=>midout<="ZZZZZZZZZZZZZZZZ";

end case;

if(alu_function="000" or "001")

    if(a_in(15)="1" and b_in(15)="1" and midout(15)="0") or (a_in(15)="0" and b_in(15)="0" and midout(15)="1" )

    then V<="1";

    else V<="0";

    end if;

end if;

if(alu_function="000")

then temp:="1111111111111111"-b_in-cinextend;

if temp

      c<="1";

else c<="0";

end if;

else if(alu_function="001")

  if b_in

      c<="1";

  else c="0";

  end if;

else if(alu_function="101")

c

else if(alu_function="110")

c<=a_in(0);

else c<="0";

end if;

end process;

alu_out<=midout;

end win;

  非常感谢  非常感谢

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