为什么ADC_test的cmd文件中需更改vectors段的定义才能正常下载程序?

为什么ADC_test的cmd文件中需更改vectors段的定义，才能正常下载程序?运用同一块板子，配置McBSP实验中，cmd文件vector段不用更改，就能够编译与下载成功？

我的cmd文件是这样配置的
-w
-lrts55x.lib
MEMORY
[
PAGE 0:
MMR : origin = 0000000h, length = 00000c0h
SPRAM : origin = 00000c0h, length = 0000040h
DARAM0 : origin = 0000100h, length = 0003F00h
DARAM1 : origin = 0004000h, length = 0004000h
DARAM2 : origin = 0008000h, length = 0004000h
DARAM3 : origin = 000c000h, length = 0004000h
SARAM0 : origin = 0010000h, length = 0004000h
SARAM1 : origin = 0014000h, length = 0004000h
SARAM2 : origin = 0018000h, length = 0004000h
SARAM3 : origin = 001c000h, length = 0004000h
SARAM4 : origin = 0020000h, length = 0004000h
SARAM5 : origin = 0024000h, length = 0004000h
SARAM6 : origin = 0028000h, length = 0004000h
SARAM7 : origin = 002c000h, length = 0004000h
SARAM8 : origin = 0030000h, length = 0004000h
SARAM9 : origin = 0034000h, length = 0004000h
SARAM10 : origin = 0038000h, length = 0004000h
SARAM11 : origin = 003c000h, length = 0004000h
SARAM12 : origin = 0040000h, length = 0004000h
SARAM13 : origin = 0044000h, length = 0004000h
SARAM14 : origin = 0048000h, length = 0004000h
SARAM15 : origin = 004c000h, length = 0004000h
CE0 : origin = 0050000h, length = 03b0000h
CE1 : origin = 0400000h, length = 0400000h
CE2 : origin = 0800000h, length = 0400000h
CE3 : origin = 0c00000h, length = 03f8000h
PDROM : origin = 0ff8000h, length = 07f00h
VECS : origin = 0ffff00h, length = 00200h /* reset vector */
]

SECtiONS
[
vectors : [] > VECS PAGE 0 /* interrupt vector table */
.cinit : [] > SARAM0 PAGE 0
.text : [] > SARAM1 PAGE 0
isrs : [] > SARAM2 PAGE 0
.stack : [] > DARAM0 PAGE 0
.sysstack: [] > DARAM0 PAGE 0
.sysmem : [] > DARAM1 PAGE 0
.data : [] > DARAM1 PAGE 0
.bss : [] > DARAM1 PAGE 0
.const : [] > DARAM1 PAGE 0
.coeffs : [] > DARAM2 PAGE 0
.dbuffer : [] > DARAM3 PAGE 0
files : [] > DARAM2 PAGE 0 /* User-defined sections */
statvar : [] > DARAM2 PAGE 0
statarry : [] > DARAM2 PAGE 0
tempvar : [] > DARAM2 PAGE 0
temparry : [] > DARAM2 PAGE 0
sounds : [] > SARAM3 PAGE 0
]

运行ADC_test时，编译与load都能够成功，报错弹出窗口是  Data verification failed at address 0xFFFF00  Please verify target memory and memory map  
更改vector段的定义到其它RAM，比如vectors : [] > SARAM1 PAGE 0 /* interrupt vector table */    程序就能正常运行，
而运行UART程序时，无需更改vector段的定义，无报错信息，程序能够正常运行。