STM8S等待状态循环确认多少指令？

帕维尔，
 
 将STM8内核计时到24 MHz可以提高性能，但实际增益会因应用而异，必须使用示波器进行测量，因为STM8流水线和XFLASH的32位宽总线混淆了任何时钟周期数。
 
 当内核以24 MHz运行时，XFLASH无法如此快速地响应STM8内核。因此需要等待状态。
 当添加等待状态时，每个XFLASH访问在24 MHz时大约需要83 ns，但这种减速可能不会影响性能，因为返回了四个字节。
 如果您的代码包含占地面积小的操作码（例如，INC A，MUL X，A DIV XY等单字节指令），则没有真正的XFLASH性能损失，因为XFLASH数据提取为STM8解码流水线提供了足够的数据并且这种惩罚平均最多四条指令。
 当XFLASH不是瓶颈时，处理速度肯定会有所增加，但正如我之前所写，这种增益取决于你的代码。
 在我看来，如果你需要更多的计算能力，你可以选择STM32，或者如果你只需要很小的速度改进，你可以重新编码你的算法。
 您也可以从RAM（不需要等待状态）执行代码，但这样做的代码和数据管道必须共享同一个只有8位宽的总线。
 在我看来，16 MHz时钟是更好的选择。
 
 问候，
 
 EtaPhi



以下为原文





Pawel,

clocking the STM8 core to 24 MHz may improve performance, but the real gain changes from application to application and must be measured with an oscilloscope because the STM8 pipeline and the 32 bit wide bus of XFLASH muddle any clock cycle count.

When the core is running at 24 MHz, XFLASH can't respond to STM8 core so quickly. A wait state is therefore needed.
When a wait state is added, each XFLASH access takes about 83 ns @ 24 MHz, but this slowdown may not impact performance, as four bytes are returned.
If your code consists in small footprint opcodes (eg. one-byte instructions like INC A, MUL X,A DIV X.Y etc) there is no real XFLASH performance penalty since a XFLASH data fetch provide enough data to the STM8 decode pipeline and this penalty is averaged on at most four instructions.
When XFLASH isn't a bottleneck, there is a sure gain in processing speed but this gain, as I wrote before, depends on your code.
In my opinion, if you need more computing power, you may choose a STM32 or if you need only small speed improvements, you can recode your algorithms.
You can also execute your code from RAM (which doesn't need a wait state), but doing so the code and data pipelines must share the same bus which is only 8 bit wide.
In my opinion, a 16 MHz clock is a better choice.

Regards,

EtaPhi