怎么在FPGA上预分配引脚

只要你不尝试运行你的逻辑太接近频率限制了
您可以根据需要分配引脚。
但是可能会有一些
引脚放置问题可能会对您的时序产生负面影响。
我从来没有遇到过问题
在这些部件中实现完全布线设计，因此您没有这种分区
例如，您可能会遇到旧CPLD可能遇到的问题。
一些指示：
您要用作时钟或锁存器使能的任何信号都应该在全局时钟引脚上。
如果你有任何需要快速通过FPGA运行的组合逻辑，
将其输入和输出放在彼此附近，以减少路由延迟。
请仔细阅读用户指南，确保您没有尝试混合不兼容
IO标准，并将适当的电压连接到每个银行的Vcco。
在编写任何FPGA代码之前，我已经完成了许多电路板设计
当我使用一些更深奥的功能时，只会遇到麻烦
双向DDR信号。
对于没有DDR内存或高速的简单设计
I / O你应该能够自信地设计而无需FPGA的最终设计
内部功能。
问候，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

As long as you don't try to run your logic too close to the frequency limitation of the
device you can pretty much assign pins as you want.  However there may be some
pin placement issues that can adversely affect your timing.  I have never had problems
achieving a fully routed design in these parts, so you don't have the kind of partitioning
problems you might get with older CPLD's for example.  Some pointers:
 
Any signal you want to use as a clock or latch enable should go on a global clock pin.
 
If you have any combinatorial logic that needs to run quickly going through the FPGA,
place its inputs and outputs near eachother to reduce routing delays.
 
Read the user guide carefully to make sure you are not trying to mix incompatible
IO standards, and connect the appropriate voltage to each bank's Vcco.
 
I have done many board designs before any FPGA code was written and usually
only got into trouble when I was using some of the more esoteric functions like
bidirectional DDR signals.  For a simple design without DDR memory or high-speed
I/O you should be able to design confidently without a final design of the FPGA
internal functions.
 
Regards,
Gabor
-- GaborView solution in original post

只要你不尝试运行你的逻辑太接近频率限制了
您可以根据需要分配引脚。
但是可能会有一些
引脚放置问题可能会对您的时序产生负面影响。
我从来没有遇到过问题
在这些部件中实现完全布线设计，因此您没有这种分区
例如，您可能会遇到旧CPLD可能遇到的问题。
一些指示：
您要用作时钟或锁存器使能的任何信号都应该在全局时钟引脚上。
如果你有任何需要快速通过FPGA运行的组合逻辑，
将其输入和输出放在彼此附近，以减少路由延迟。
请仔细阅读用户指南，确保您没有尝试混合不兼容
IO标准，并将适当的电压连接到每个银行的Vcco。
在编写任何FPGA代码之前，我已经完成了许多电路板设计
当我使用一些更深奥的功能时，只会遇到麻烦
双向DDR信号。
对于没有DDR内存或高速的简单设计
I / O你应该能够自信地设计而无需FPGA的最终设计
内部功能。
问候，
的Gabor
-  Gabor



以下为原文

As long as you don't try to run your logic too close to the frequency limitation of the
device you can pretty much assign pins as you want.  However there may be some
pin placement issues that can adversely affect your timing.  I have never had problems
achieving a fully routed design in these parts, so you don't have the kind of partitioning
problems you might get with older CPLD's for example.  Some pointers:
 
Any signal you want to use as a clock or latch enable should go on a global clock pin.
 
If you have any combinatorial logic that needs to run quickly going through the FPGA,
place its inputs and outputs near eachother to reduce routing delays.
 
Read the user guide carefully to make sure you are not trying to mix incompatible
IO standards, and connect the appropriate voltage to each bank's Vcco.
 
I have done many board designs before any FPGA code was written and usually
only got into trouble when I was using some of the more esoteric functions like
bidirectional DDR signals.  For a simple design without DDR memory or high-speed
I/O you should be able to design confidently without a final design of the FPGA
internal functions.
 
Regards,
Gabor
-- Gabor

你应该为Xilinx工作！
感谢您的回复Gabor。
我将开始设计电路板，而不是浪费时间设计硬件，更多的时间将进入软件



以下为原文

You should work for Xilinx!
Thanks for your response Gabor.
 
I will start designing boards, instead of wasting time designing hardware, more time will go into the software

我希望你不要认为硬件设计浪费时间。
祝你好运
你的项目。
问候，
的Gabor
-  Gabor



以下为原文

I hope you don't consider hardware design a waste of time.  Good luck on
your project.
 
regards,
Gabor
-- Gabor

我的意思是“浪费”时间，因为我使用XC9572，然后是2x XC9572，现在是Spartan 2，在以前的硬件设计上经历了3次迭代.XC2S100E将在最终设计中取代这些CPLD



以下为原文

I meant "wasting" time in a sense that I've been through 3 iterations on previous hardware designs using the XC9572, then 2x XC9572, now Spartan 2. The XC2S100E  will replace these CPLD's in the final design

而且，再次感谢你！



以下为原文

And, Thank you again!

wirewrapper写道：
我的意思是“浪费”时间，因为我使用XC9572，然后是2x XC9572，现在是Spartan 2，在以前的硬件设计上经历了3次迭代.XC2S100E将在最终设计中取代这些CPLD
虽然Spartan 2e很容易取代几个9572 CPLD中的逻辑，但id不会
在这样做时遇到路由问题，请记住存在根本差异
这些家庭之间。
FPGA需要时间进行配置，因此您需要采用它
如果它用于系统启动控制，则考虑在内。
你也失去了更简单的确定性
引脚到CPLD的时序。
如前所述，如果你有任何异步路径
通过FPGA，您应该保持引脚接近，以最大限度地减少布线延迟。
也
你知道Spartan 2e系列与Spartan 2（没有E）不同，不是5V
宽容？
问候，
的Gabor
-  Gabor



以下为原文

 

wirewrapper wrote:
I meant "wasting" time in a sense that I've been through 3 iterations on previous hardware designs using the XC9572, then 2x XC9572, now Spartan 2. The XC2S100E  will replace these CPLD's in the final design

 
While the Spartan 2e will easily replace the logic in several 9572 CPLD's, and id won't
run into routing issues in doing so, remember that there are fundamental differences
between these families.  The FPGA requires time to configure, so you need to take that
into account if it is used for system start-up control.  Also you lose the simpler deterministic
pin to pin timing of the CPLD's.  So as I said before if you have any asynchronous paths
through the FPGA you should keep the pins close to minimize the routing delays.  Also
you are aware that the Spartan 2e series, unlike Spartan 2 (without the E), is not 5V
tolerant?
 
Regards,
Gabor
-- Gabor

gszakacs写道：
...你也失去了更简单的确定性
引脚到CPLD的时序。
......还有
你知道Spartan 2e系列与Spartan 2（没有E）不同，不是5V
宽容？...
谢谢你的澄清。
我选择了“E”版本，因为家庭数据表说它是“专用的”逻辑。
我将主要用于逻辑，触发器/锁存器和计数器。
还有可能使用512bx8同步RAM，这就是我从CPLD跳转到Spartan 2 FPGA的原因。
我确实牺牲了5V耐受性，因为我已经读过有人声称要承受5V I / O容量但与5V器件完全不兼容的3.3V输出信号问题的人，即它们是5V输入容忍但不是5V输出
宽容。



以下为原文

 

gszakacs wrote:

 ... Also you lose the simpler deterministic
pin to pin timing of the CPLD's. .... Also
you are aware that the Spartan 2e series, unlike Spartan 2 (without the E), is not 5V
tolerant?...

 
Thanks for clarifying.
 
I chose the "E" version because the family datasheet says it is "specialized" for logic. I will be using it for mainly logic, flip-flops/latches, and counters. There is also a possibility of using the 512bx8 synchronous RAM, which is why I have made the jump to a Spartan 2 FPGA from CPLD.
I did sacrifice 5V tolerance because I have read of people having issues with 3.3V output signals from devices claiming to be 5V I/O tolerant, but are not fully compatible with the 5V devices, i.e. they are 5V input tolerant, but not 5V output tolerant.
 

实际上绝大多数5V逻辑器件的输入阈值接近1.6V和
一分钟
2.0V的规格这使它们与原来的双极性兼容
TTL家族。
Spartan FPGA的LVCMOS或LVTTL输出将驱动为高电平
非常接近3.3V电源轨。
所以你应该能够直接与
5V器件输入。
话虽这么说，你应该经常检查数据表
你正在使用的设备。
一些5V CMOS器件具有更高的输入阈值，
通常在2.5V左右，输入端具有滞后的设备可以有一个
Vih高阈值等于或高于3.3V。
那些显然不适用于正常情况
Spartan 2 LVCMOS或LVTTL输出。
但是，因为Spartan 2具有5V容限
您可以在Spartan 2（非E）上使用开漏输出，上拉至+ 5V。
问候，
的Gabor
-  Gabor



以下为原文

Actually the vast majority of 5V logic devices have an input threshold near 1.6V and
a Vih min. specification of 2.0V  This makes them compatible with the original bipolar
TTL families.  An LVCMOS or LVTTL output from the Spartan FPGA will drive high
very close to the 3.3V power rail.  So you should be able to interface directly with the
5V device inputs.  That being said, you should always check the data sheet of the
device you are using.  Some 5V CMOS devices have much higher input thresholds,
usually around 2.5V and devices that have hysteresis on the inputs can have a
Vih high threshold at or above 3.3V.  Those would clearly not work with the normal
Spartan 2 LVCMOS or LVTTL outputs.  However, because Spartan 2 is 5V tolerant
you could use open-drain outputs with pullup to +5V on the Spartan 2 (not E).
 
Regards,
Gabor
 
-- Gabor

我有几个星期才开始使用XC2S100或XC2S100E。
我打印出Spartan 2非“E”版本系列数据表（我更喜欢打印）。
我还将打印Spartan 2“E”系列数据表，并进行比较。
你让我重新思考并观察我通常不会检查的规格，（比听网络谣言更好）。
我在这个项目中只有很少的IC，所以这些规格很容易检查。
再次感谢！



以下为原文

I have a few weeks before I commit to an XC2S100 or an XC2S100E. I have the Spartan 2 non "E" version family datasheet printed out (I prefer printed). I'll print the Spartan 2 "E" family datasheet as well, and compare them.
 
You have made me rethink and observe spec's I'm not usually checking, (better than listening to internet rumors). I have very few IC's in this project, so these spec's will be easy to check.
 
Thanks again!