在设置引脚时遗漏了一些东西

当你连接到引脚控制登记compunent不会正常工作，当你试图把oututs与直接写入端口。您可以发布您的完整的项目，这样我们都可以在你所有的设置，看看吗？这样做，使用的创造者- >；文件& gt；创建工作包（最小的）并将结果文件。鲍勃



     以下为原文
  When you connect a control register to a pins compunent it won't work properly when you try to set the oututs with a direct write to the port. Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.



Bob
 

如果（CythGETYGR32）（CyrGeGrpT11PS）！＝0）断裂；
和这个不一样
寄存器R32 var＝CythGETYRG32（CyrGeRePrt1PPS）；
如果（var）！＝0）断裂；
第一个是快8倍左右。
查看编译器生成代码的LST文件会很有启发性。
差异。我在另一个处理器中发现问题，发现任何
本地大小类型最好用指针来处理速度/代码大小的原因。
通过这样做能够获得大量的代码减少代码。
问候，Dana。



     以下为原文
  if( CY_GET_REG32(CYREG_PRT1_PS) != 0 ) break;
    is not the same as this
    register r32 var = CY_GET_REG32(CYREG_PRT1_PS);
    if( var != 0 ) break;
    The first one is about 8x faster.
     
    It would be instructive to look at .lst file for the compiler generated code
    differences. I had issues in another processor and found that any non
    native size type was best handled with pointers for speed / code size reasons.
    Was able to get a lot of code reduction thruout code by doing that.
     
    Regards, Dana.

这里是一个AP笔记，讨论快速PIN切换问题，其中之一
GPIO的东西。
HTTP://www. CyPress？COM/？RID＝93401 AN864—PSOC®4 -使用GPIO引脚
问候，Dana。



     以下为原文
  Here is an ap note that discusses fast pin toggle issues, amongst other
    GPIO stuff.
     
        
              
    http://www.cypress.com/?rID=93401     AN86439 - PSoC® 4 - Using GPIO Pins
     
     
    Regards, Dana.

80兆赫部件



     以下为原文
  The 80 Mhz parts -
     
     

嗨，鲍伯
我附上了这捆，谢谢你看一看。
嗨，Dana
这是一个神秘的文档，它显示了Ion不需要把东西连接到PIN上。我希望鲍伯发现我做错了什么。
是否记录了ARM能将数据泵到内部FIFO缓冲器的速度？它能把数据推到48兆赫，然后让硬件在48兆赫推出吗？
AcycjdSP.CyWrk.CaseV01.Zip
202.3 K



     以下为原文
  Hi Bob
    I have attached the bundle, thanks for having a look.
     
    Hi Dana
    That is the mythical document that shows I don't need to connect things to pins for it to build.. I hope Bob finds what I have done wrong.
     
    Is it documented on how fast the ARM can pump data to the internal FIFO buffers? Can it push data there at 48Mhz, and then let the hardware push it out at 48Mhz?

•   AsyncJDSP.cywrk.Archive01.zip 202.3 K  
  
  

但是，80MHz的芯片有更快的GPIOSPEDE还是CPULT停机时间更长？DOCS显示它只有一个简单的切换周期为500 +ns。
DMACONDRONTROR可能能够帮助，但可能需要很长时间才能建立，因为它看不到寄存器，所以寄存器状态将需要写入RAM（它是否具有延迟状态？）然后DMAd到别针。它运行的时钟速度是多少？
问题不是！＝0，但事实上有2条线。我会为你拆卸拆卸的。



     以下为原文
  But do the 80mhz chips have faster GPIO speeds or does the CPU just stall for longer? The docs show it has a period of 500+ns on just a simple toggle.
    The DMA controller might be able to help, but it might take to long to set up as it can't see the registers, so the register state will need to be written to RAM( does it have delay states? ) then DMAd to pins. What clock speed does it run at?
     
    The issue was not the != 0 but the fact there are 2 lines. I will pull the disassembles for you tommorow.

好，回到绘图板：
您不需要使用状态寄存器来读取PIN的状态。
您不需要使用控制寄存器来设置PIN的状态。
你不能把一个PIN与一个内部信号相连接，并用软件来预测PIN，期望得到一个可预测的结果（谁会赢，信号电平还是书面值）？？？）
浅谈如何快速引脚可切换的软件已经开始经常（开始psoc1），总是在下面的结论：
你可以切换一个引脚在可比低速4MHz（让它多或少，不管）但你不能控制引脚因为您使用了整个CPU的性能切换。
相反，一个简单的部件，是真正的硬件在PSoC的你可以在48mhz肘节销依然能够控制启动/停止，脉冲宽度，保持一个串行接口和模数转换器等而只使用较少的CPU功率。
是的，我承认，这是很有诱惑力的写引脚切换程序测试MCU性能但是，通常你不会将一个印地赛车的性能，通过比较它们的负载能力小。
我建议你尝试解决一些实际问题作为一个反射光的屏障，检测或调节和其他项目通常可以找到在嵌入式微系统的世界。然后你会看到PSoC能做什么。
快乐设计
鲍勃



     以下为原文
  OK, back to the drawing-board:
    You do not need to use a status register to read the state of a pin.
    You do not need to use a control register to set the state of a pin.
    You cannot conect a pin to an internal signal and write to the pin by software expecting a predictable result (Who will win, the signal level or the written value???)
     
    The discussion on how fast a pin can be toggled by software has been started often (started with PSoC1) and always ended up in the following conclusion:
    You can toggle a pin at a comparable low speed as 4MHz (let it be more or less, no matter) but you cannot control the pin since you are using up the whole CPU performance to toggle.
    Instead, with a simple component which is real hardware inside a PSoC you may toggle a pin at 48MHz and still being able to control start/stop, pulse width, maintainig a serial interface and some ADCs etc while using only a small amount of CPU power.
     
    Yes, I admit, it is tempting to write a pin-toggle program to test the performance of an MCU, But, you normally do not compare the performance of an Indy-Car to a pickup by comparing their load capacity.
     
    I would suggest you to try solving some real-world problems as a reflex light barrier, sensing or regulating and other projects you usually find in the world of embedded microsystems. Then you will see what a PSoC can perform.
     
    Happy designing
    Bob

对于速度，参见CY8C58XXX数据表中的AC规范。
没有必要为你的代码复制ASM，我看到了。
鲍勃



     以下为原文
  For speeds see AC specs in datasheet for CY8C58xxx .
    No need to copy the ASMs for your given code, I saw that.
     
    Bob

更多信息：
当你删除你的控制和状态寄存器和连接线
核对“硬件连接”，你可以用剩下的两销组件
fromcpld_read()在下两位的结果同时得到两输入引脚的值
tocpld_write()要同时写入所有的5引脚（不同的）价值。
在您的PSoC4上没有DMA
当你需要DMA，你需要购买一个cy8ckit-044与psoc4 - M芯片有DMA
鲍勃



     以下为原文
  Some more info:
    When you delete your control- and status-registers and the connecting wires
    and check off the "Hardware Connection" for your remaining two pin-components you may use
    fromCPLD_Read() to get both input pins values at the same time in the lower two bits of the result
    toCPLD_Write() to simultanously write to all 5 pins a (different) value.
     
    There is no DMA on your PSoC4
    When you need DMA, you will have to purchase a CY8CKIT-044 with a PSoC4 -M. That chip has got DMA
     
    Bob

这是一个神秘的文档，它显示了Ion不需要把东西连接到PIN上。我希望鲍伯发现我做错了什么。
每个引脚有一个内部寄存器，一个位在其相应端口，XXXYDR寄存器，与之关联。
所以，你不需要一个控制装置来驱动它。
是否记录了ARM能将数据泵到内部FIFO缓冲器的速度？它能把数据推到48兆赫，然后让硬件在48兆赫推出吗？
在AP注释中，直接写入寄存器的引脚切换率为300 kHz。
你可以通过查看循环次数来快速检查任何设备。
做两个ASM MOV IMMEDATIATE与一个近跳，这将反映代码驱动
切换速率。
问候，Dana。



     以下为原文
  That is the mythical document that shows I don't need to connect things to pins for it to build.. I hope Bob finds what I have done wrong.
     
    Each pin has an internal register, a bit in its respective port, the xxx_DR register, associated with it.
    So no you do not need a control reg to drive it.
     
     
     
    Is it documented on how fast the ARM can pump data to the internal FIFO buffers? Can it push data there at 48Mhz, and then let the hardware push it out at 48Mhz?
     
    In the ap note direct write to the register maxes out at a pin toggle rate of ~ 300 Khz.
    You can always do a quick check on any device by looking at the number of cycles
    to do two ASM mov immeadiates coupled with a near jump, that will reflect code driven
    toggle rates.
     
    Regards, Dana.

下面是一个将HFCLK直接输出到48 MHz的PIN的例子。
不是最漂亮的波形，而是它的波形。
问候，Dana。



     以下为原文
  Here is an example of putting a HFCLK driectly out to pin, 48 Mhz.
    Not the prettiest looking waveform, but its there.
     
   
     
    Regards, Dana.
     
     

检查“硬件连接”
这就是我遗漏的东西：“把它拿走，我不需要其他东西。”
我建议你尝试解决一些现实世界的问题。
我正在处理一个现实世界的问题。该代码不只是切换一些引脚闪烁LED超快，它只是针切换现在，作为婴儿的步骤。
步骤1。由于臂不能捕获8MHz的脉冲，所以在CPLDWork中，我的异步设置复位。因此，等待一个PIN从CPLD（调用动作）高到另一个引脚的切换（告诉CPLDigoT，并因此清除它的SR）。
步骤2。我能及时反应并把地址加到千里之外吗？
步骤3。可以IDO连续5次，每次地址
步骤4。我能及时反应并计算地址和数据值，把它推到手臂上，在1000纳秒？
步骤5。可以IDO连续11次，并每次地址和拉一个不同的字节
步骤6。或者可以在时间、Calc和地址上进行反应，然后等待完成，然后从CPLD中拉取数据值，及时作出反应，给出下一个地址。
…测量小步
通过调整优化水平，我设法赢得与编译器认为战斗（为什么它与优化设置为高，释放和ideclare的登记是登记rg32是在堆栈中保存的值再次读取下一个时钟）我一直能够反应To在240nS的CPLDL请求行，然后执行脉冲为100NS
LDR指令/ SDR是2钟，在48mhz，~ 41ns所以有等待状态的总线延迟到100ns？你要等那么长的时间，或者如果你把其他指令，注册/注册或注册/ #之间将他们的cpustalling执行？
当你需要DMA，你需要购买一个cy8ckit-044与psoc4 - M芯片有DMA
我不能找到一个DMAmodule的技术规范，为psoc4-m我搜索trmand网站才恢复正常psoc4，我找到一个家庭指导说明dmaon框图，但没有技术规格。我搜索的应用笔记DMA一无所获，你知道一个文件的细节，它的运作？
在美联社注意直接写入登记最少一个~ 300kHz引脚触发率。
示波器照片是这样显示的吗？没有一个我不太擅长阅读它们。
花时间帮助我，谢谢，我真的很感激，特别是你的周末。



     以下为原文
  check off the "Hardware Connection"
    That is what I was missing :) take that off and I don't need the other things.
    I would suggest you to try solving some real-world problems
    I am working on a real world problem. The code is not just toggle some pins to blink a led super fast, it is only pin toggles for now, as baby steps.
    Step 1. Since the arm can not trap a 8Mhz pulse does my Async SetReset in the CPLD work. Hence the wait for a pin  to go high from the CPLD ( the call to action ) then the toggle of another pin ( tell the CPLD I got it, and to hence clear its SR ).
    Step 2. Can I react in time and calc an address, push it to the arm, in 1000ns?
    Step 3. Can I do that 5 times in a row and inc the address each time
    Step 4. Can I react in time and calc an address, and a data value, push it to the arm, in 1000ns?
    Step 5. Can I do that 11 times in a row and inc the address and pull a different byte each time
    Step 6. Or can I react in time, calc and address, then wait for the Done, then pull the data value from the CPLD, react to it in time to give the next address?
    ..... I like to take small measured steps
    By tweaking the optimisation levels, I have managed to win the fight with the compiler I think ( Why does it in release with optimisation set to high, and I declare the register to be 'register rg32' does it save the value on the stack to read again the next clock ) I have been able to get it to react to the CPLD_request line in ~240ns then do a pulse for ~100ns
    The LDR/SDR instruction is 2 clocks, at 48mhz that is ~41ns so there are wait states in the bus to delay it to 100ns? Do you have to wait that long or if you put other instructions that are reg/reg or reg/# in between will they execute instead of the CPU stalling?
    When you need DMA, you will have to purchase a CY8CKIT-044 with a PSoC4 -M. That chip has got DMA
    I can't find a tech spec for the DMA module, I searched for PSoC4-M TRM and the site only returned the normal PSoC4 one, I did find a family guide which showed the DMA on the block diagram, but no tech specs. I searched for app notes on DMA got nothing, do you know of a document that details its workings?
     
    In the ap note direct write to the register maxes out at a pin toggle rate of ~ 300 Khz.
    Is that what the osciliscope pictures show? Not having one I'm not very good at reading them.
     
    Thanks for taking time to help me, I really appreciate it, especially on your weekends.

PSoC5文档不直接引用等待状态，但是如果第一个32 K的SRAM可以用来运行代码，那么它可以全速运行，它意味着如果代码不在SRAM中，则运行速度较慢。因为它的时钟是80MHz，也许Flash就是无法处理它。
失踪60ns以上是否是由于闪光？正如Dana已经证明的引脚可以运行在48 MHz，我们假设CPU核心运行在48 MHz，两个商店到同一地点，即时值不应导致任何管道摊位，阅读摊位或管道冲洗，没有缓存刷新。取指令花费我们60ns吗？开发了一个pWMTimeMT模块来对某些代码进行一次中断，但这有助于错误MSG。
错误：MPR.M0139：时钟输入“TimeRy1：CysM0S8YTCPWMY1：时钟”的无效连接：时钟从“时钟锁：DSIIN 0”驱动。该组件需要来自时钟块的时钟。（APP＝CysFIT）
“时钟块：DSIIN 0”不是来自时钟块吗？
看到PSoC5S是15美元，有一种方法可以找到；）我通常的供应商不存储PSoC 5包，所以我开始寻找另一个，这不会杀死我的邮资。它的严格的电力清洁可能使它不去，但它似乎也不能/将难以在2层PCB上使用。



     以下为原文
  The PSoC 5 documentation doesn't directly reference wait states, but given the first 32K of SRAM can be used to run code, so it can run at full speed, it does imply that if the code is not in SRAM it runs slower. Seeing as its clock is 80Mhz, maybe Flash just can't handle it.
    Could the missing 60ns above be due to FLASH? As Dana has proven the Pins can run at 48Mhz, we assume the CPU core is running at 48Mhz, two stores to the same location with immediate values shouldn't cause any pipeline stalls, read back stalls or pipeline flushes, there is no cache to flush. Is the instruction fetch costing us the 60ns. I tried to make a PWM timer module to fire an interrupt to time some code but I got this helpful error msg
    Error: mpr.M0139: Invalid connection for clock input "Timer_1:cy_m0s8_tcpwm_1:clock" driven from "ClockBlock:dsi_in_0". The component requires a clock from the clock block. (App=cydsfit)
    "ClockBlock:dsi_in_0" is not from the Clock Block?
     
    Seeing as the PSoC5s are $15 I guess there is one way to find out ;) My usual supplier doesn't stock the PSoC 5 kits so I  have started looking for another, that doesn't kill me on postage. Its stringent power cleanliness might make it a no go though, also it seems like it can't/will be difficult to use on a 2 layer PCB.

PSoC 4可能不像你需要的那么快…
但是等等…
在你的PSoC中有4个UDB，它包含两个FIFO和一个可编程的ALU，一个计数器，一些PLD，所有的24MHz都很容易运行。所以问题仍然存在：你能用硬件解决你的问题吗？
“计算地址”是什么意思？
你对我的要求似乎还不太清楚。
鲍勃



     以下为原文
  The PSoC 4 might not be as fast as you need it to be...
    But wait..
    There are 4 UDBs within your PSoC with a DataPath object containing two FIFOs and a programmable ALU, a counter some PLD and all is running easily at 24MHz. So the question still remains: Can you do your problem in hardware?
    What do you mean with "Calculatinng an address"?
    All your requirements seem not yet quite clear to me.
     
    Bob

好啊
CY8CKIT-059 PSOC5LP试剂盒
检测和响应脉冲240Ns -与PSOC4相同的时间
脉冲长度60ns～40ns比PSOC4快
这是时钟设置为74.7MHz。我还没看过SRAMORT中如何运行代码，也许这会让我在PSoC4上运行速度更快？
此外，必须检查缓冲区的输入，否则代码根本不会影响输入引脚状态，这个缓冲区能解释为什么它不快吗？



     以下为原文
  Ok
    CY8CKIT-059 PSOC 5LP kit
    Time to detect and respond to a pulse 240ns - same as the PSOC4
    Pulse length 60ns - 40ns faster than PSOC4
     
    This is with the clocks set to 74.7MHz. I have not looked at how to run code in the SRAM yet, maybe that will give me speed over the PSOC4?
    Also I must have the buffer checked on input otherwise the code won't detech the input pin state at all, could this buffer explain why it is no faster?

因此给出以下步骤
将低8位地址放在总线上
告诉CPLD它在那里
告诉CPLD上8位地址在总线上
将高位8位地址放在总线上
告诉CPLD，8位数据在总线上
把8位数据放到总线上
告诉CPLD完成
把Xis的CPLD放在PLD部件上的计数器上可以做，并且保存~300纳秒。这就是为什么我想知道CPUTO FIFOWAS是否更快，因为它可以把数据放入FIFO，并让CPLD脉冲ARM FIFO获得数据离开CPUFLIP。
这需要做什么？
有3个组成部分：计算机、CPLD（处理总线封送）和PSoC。
1）8向屏幕滚动
所以你有一个40x25字符屏幕= 1000字节
滚动你需要做的
屏幕基数=屏幕基数+ 1
屏幕基数+ 1 =屏幕基数+ 2
…
屏幕基数+ 38 =屏幕基数+ 39
屏幕基数+ 40 =屏幕基数+ 41
…
向下滚动你需要做的事情
屏幕基数+ 960 =屏幕基数+ 920
屏幕基数+ 961 =屏幕基数+ 921
…
屏幕基数+ 880 =屏幕基数+ 920
…
向左滚动
屏幕基数=屏幕基数+ 41
屏幕基数+ 41 =屏幕基数+ 82
…在对角线上，移位次数为0～46回到0。
因此，当硬件计数器能够覆盖所有8个方向时，大量的硅在CPU中是微不足道的。
然后你必须用颜色记忆来做同样的事情。
你也必须能够告诉ARM屏幕基础是什么
所以你在记忆中做一个包
C000：00 04
然后计算机告诉ARM它有C000的东西，它想要它做任务1（其中1是设置屏幕基础）。
的cpldwill负荷C000进入缓冲区的地址然后通过任务数的手臂，armthen看到它是任务，然后指示cpldto那个地址读的第一个字节，并给它，它的商店，公司在CPLDand的地址缓冲说获得下一个字节，CPLD的获取B年，然后给它的手臂，手臂存储在RAM，并告诉cpldto给电脑控制了。
然后计算机将信号cpldwith另一任务2（滚动屏幕左1字符）。cpldtells手臂的任务，手臂告诉cpldto采取控制，然后给它上面的第一个地址，并读取字节。然后第二个地址，告诉它写它只是读取字节…直到所有的1000完成，然后改变地址补习，不千，然后告诉cpldto给控制回主机。
一旦把计算机已经等待~ 3000ns直到它可以接管控制armdecides，有的是建立其内部状态的时间，切换任务等
精灵复用
每个精灵需要X，Y，颜色，图像，然后是1字节为8使，X Y扩大，扩大，优先级和xm***。
假设你想要32个精灵。所以手臂要拉32xs，32ys，32colours，32 32位图像，杂项-当然你需要一个任务，告诉armwhere数据保存在RAM中，而另一个任务，告诉你已经改变了它的手臂，并抓住了。一旦它抓住数据将控制返回给计算机。
的armwill然后ysort三十二精灵，和工作需要设定计算机寄存器分组，它可以有8线只有8组寄存器的精灵。它将各种所需的数据格式和建立什么样的光栅线需要写数据在内部栅格线表。
的cpldwill跟踪周期的计算机，从而能够猜当栅格点会发生。一些时间~五计算机时钟的前栅格线即将来袭，该armwill采取控制通过CPLD，告诉它要d012美元和调查它的价值直到它击中正确的价值。一旦点击右边的值会写8雪碧的数据在内存中的正确的地方，告诉cpldto让主机控制然后告诉CPLDthe下光栅线希望（以及栅格线几次）
有些计算机模型有65周期每线，约64，其他63，所以armwill需要一个任务，让其查询，或时间机器的工作，是哪一个。
翻转精灵数据。
精灵是63字节数据和颜色的两位大翻转是不平凡的。告诉armwhere是在RAM中，它可以在63个字节，然后读取翻转比特的正确方法，然后回写63字节。
块移动，减压algortims，写样本数据到语音芯片…许多其他的东西
计算机让你有一半的1MHz总线。所以，钟1000ns只有500ns，所以有效2mhz。（PALmachines给你1015ns ntscmachines给你977ns）
在你需要设置地址有效500ns的开始，最后你要么设置数据或读取，这取决于你如何设置的R / wline数据。所以这给500ns窗口获取地址的CPLD，Ithen 70ns之后，得到的R / wline状态，那么我400ns获取数据的cpldif需要写入数据。一旦数据的cpldihave直到1000ns为准备下一轮。
所以基本上我需要一个CPU的全部力量，我需要至少2K的RAM，Flash存储程序/舞会。有额外的pldand的aluunits是一个不错的奖金，我希望我能把循环计数器来跟踪光栅线和位置为他们。



     以下为原文
  so given the following steps
    put lower 8 bits of address onto bus
    tell cpld it is there
    tell cpld that the upper 8bits of address are on the bus
    put upper 8 bits of address onto bus
    tell cpld that the 8 bits of data are on the bus
    put 8bits of data onto bus
    tell cpld done
    Putting the tell cpld that X is there into a counter on the PLD parts could be done and save ~300ns I think. This is why I wanted to know if the CPU to FIFO was faster as it could put the data into the FIFO and let the CPLD pulse the ARM FIFO to get the data leaving the CPU free.
     
    What does this need to do...
    There are 3 components a Computer a CPLD ( to handle the bus marshaling ) and the PSoC
    1.) 8 way screen scrolling
    so you have a 40x25 char screen = 1000 bytes
    to scroll it left you need to do
    screenBase = screenBase + 1
    screenBase +1 = screenBase + 2
    ...
    screenBase + 38 = screenBase + 39
    screenBase + 40 = screenBase + 41
    ....
    to scroll down you need to do
    screenBase + 960 = screenBase + 920
    screenBase + 961 = screenBase + 921
    ....
    ScreenBase + 880 = screenBase + 920
    ...
    to scroll up left
    screenBase = screenBase + 41
    screenBase + 41 = screenBase + 82
    ... being diagonal the number of shifts goes for 0-46 back to 0
    So while that can be done with hardware counters to cover all 8 directions is a lot of silicon, in a CPU - trivial.
    Then you have to do the same with colour memory.
    You also have to be able to tell the ARM where screenBase is
    so you make a packet in memory like so
    c000 : 00 04
    Then the computer tells the ARM that it has something at C000 for it, and that it wants it to do task 1 ( where 1 is set Screen Base )
    The CPLD will load C000 into its address buffer and then pass the task number to the ARM, the ARM then see that it is task1, it then instructs the CPLD to read the first byte at that address, and give it to it, it stores in, inc the address buffer in the CPLD and says get the next byte, cpld gets the byte and then gives it to the ARM, arm stores that in its RAM, and tells the CPLD to give the computer control again.
    Then later the computer will signal the CPLD with another task 2 ( scroll screen left 1 char ). The CPLD tells the ARM task 2, the ARM tells the CPLD to take control, and then gives it the first address from above, and to read that byte. Then the 2nd address, tells it to write the byte it just read... until all 1000 are done, then changes the address to CRAM, does the 1000, then tells the CPLD to give control back to the host.
     
    Once the ARM decides to take control of the computer it has to wait ~3000ns till it can take over, so there is plenty of set up time for its interal state, switching on task etc
     
    Sprite Multiplexing
    each sprite needs x,y,colour,image and then there is 1 byte for all 8 on enable, x expand, y expand, priority and xm***.
    Say you want 32 sprites. so the ARM needs to pull in 32xs, 32ys, 32colours, 32 images, 32 misc bits- ofcause you will need a task that tells the ARM where the data is kept in ram, and another task that tells the arm you have changed it, and to grab again. Once it has grabbed the data it will give controll back to the computer.
    The ARM will then Y sort the 32 sprites, and work out the grouping needed to set the computers registers, it can have 8 on a line and only has 8 sets of registers for sprites. It will then arange the data to the needed format and build an internal raster line table of what raster lines it needs to write that data on. 
    The CPLD will keep track of cycles the computer has, and thus be able to guess when the raster points are going to occur. some time 4~5 computer clocks before the Raster line is about to hit, the ARM will take control via the CPLD, tell it to get the value of $d012 and poll it till it hits the right value. Once it hits the right value it will write the 8 sprite data to the right places in memory, tell the CPLD to let the host have control and then tell the CPLD the next raster line it wants ( well raster line - a few cycles )
    Some models of the computer have 65 cycles per line, some 64, others 63, so the ARM will need a task that lets it query, or time the machine to work out which one it is.
    Flip sprite data.
    Sprites are 63 bytes of data and the colours are 2 bits wide so flipping them is not trivial. Tell the ARM where it is in RAM , it can pull in the 63 bytes, then as it reads flips the bits the right way , then write back the 63 bytes.
    Blocks moves, decompression algortims, write sample data to the sound chip... lots of other things
     
    The computer lets you have half of a 1Mhz bus. So while th Clock is 1000ns you can only have 500ns, so effectivly 2Mhz. ( well PAL machines give you 1015ns NTSC machines give you 977ns )
    At the start of the 500ns you need to set the address valid, then at the end you either set the data or read that data depending on how you set the R/W line. So this gives a 500ns window to get the Address to the CPLD, I then have 70ns after that or so to get the R/W line state as well then I have 400ns to get the data to the CPLD if I need to write data. Once the data is to the CPLD I have until the 1000ns is up to prepare for the next round.
     
    So basically I need the full power of a CPU, I need at least 2K RAM, and flash/prom to store the program in. Having extra PLD and the ALU units is a nice bonus, I hope I can put the Cycles counters to track the raster line and position into them.

RAM与闪存执行（皮质M3）
CyPress公司
问候，Dana。



     以下为原文
  Ram vs Flash execution (Cortex M3) -
     
    www.cypress.com/
     
     
     
    Regards, Dana.

一个复杂的项目，我祝你好运！
鲍勃



     以下为原文
  Quite a complex project, I whish you good luck!
     
    Bob