利用切片的最佳利率是多少？

没有“安全”的利用率。
如果使用1％或100％的FPGA，设计可靠地工作。
如果您发现问题，我建议您查看您的设计。
例如，异步设计技术可能会导致毛刺和竞争条件，这些干扰和竞争条件可能在电压/温度范围，工艺和批次变化之间产生间歇性。
即使是不同的实现迭代也可以看到地点和路线不同，因此并不总是看到问题。
设计可能间歇性地工作的原因有很多，但我不认为利用率是一个因素。
您可能希望降低利用率的原因可能包括未来更新，功能添加等，如果您没有空间可能无法实现。
放置和布线也可以实现，因此您的性能（和运行时间）可能会受到影响，因为工具的操作空间要小得多，并且必须开始将越来越多的无关逻辑映射到切片或MAP /放置不太理想的东西。
这就是为什么人们倾向于认为设备利用率低于80％但是它的手指在空中并且取决于设备尺寸，留下20％未使用的MAP / PAR灵活性可能是小的或大的。
控制集的数量也可能意味着必须使用更多的设备。
合成是对利用率的估计，性能也是如此。
MAP结果将为您提供可靠的利用率数据。
我不认为在PAR中有任何进一步的优化可以改变这个数字，虽然PAR可能会使用一些LUTS等来实现路由？
其他人可能会证实这一点。
或者，为了安全起见，请使用PAR结果。
我会非常有信心使用MAP进行利用。
syntheis（和MAP）中的不同选项可能会改变切片计数。
优化选项可能是最好的例子。
您可以告诉工具以利用成本优化速度，您可以告诉工具推断某些功能的某些嵌入式块。
即，使用Block RAM而不是分布式RAM，在DSP48切片中构建多路复用器而不是切片，FSM优化等。使用这些选项来尝试达到优化和性能目标是很常见的。
有关这些科目的更多信息可以参加正式的Xilinx培训课程。
设计技巧和技巧以及性能设计将是我在这个例子中推荐的两个。
干杯
彼得
RegardsPeter BoxallManaging DirectorBlack Box ConsultingXilinx授权培训ProviderLive在线讲师带领全球培训
在原帖中查看解决方案



以下为原文

There is no 'safe' utilisation number. The design shoukd work reliably if 1% or 100% of the FPGA is utilised. If you are finding problems, I would recommend looking into your design. For example, asyncronous design techniques can cause glitches and race conditions which can be intermittent across voltage/temperature ranges, process and lot variations. Even a different implementation iteration can see the place and route differ and therefore not always see a problem. There are many reasons why a design might work intermittently but I would not expect the utilisation % to be a factor.
 
Reasons why you may want to reduce your utilisation can include future updates, feature additions etc which might not be possible if you have no space. Place and routing can also be effected and hence your perfomance (and run times) may take a hit as the tools have much less room for manuever and has to start mapping more and more unrelated logic into slices or MAP/Place things less optimal. This is why people tend to consider a device at <80% utilisation but its a finger in the air and depending on device size, leaving 20% unused for MAP/PAR flexibility can be a small or large amount.
 
The amount of control sets might also mean more of the device has to be unused.
 
Synthesis is an estimation of utilisation, as is the performance. The MAP result will give you confident figures of utilisation. I dont think there is any further optimisation done in PAR which can change this figure, although PAR might use up some LUTS etc for route-thru's perhaps? Someone else might be able to confirm this. Or, to be safe, use PAR results. I would be pretty confident using MAP for utilisation though.
 
Different options in syntheis (and MAP) can vary your slice count. Optimisation options are probably the best example of this. You can tell the tools to optimise for speed at the cost of utilisation, you may tell the tools to infer certain embedded blocks for certain features. ie, use Block RAM instead of distributed RAM, build a mux in a DSP48 slice instead of slices, FSM optimisation, etc. It is very common to play with these options to try and reach your optimisation and performance goals.
 
Futher information of these subjects can be found from attending formal Xilinx training courses. Design Tips and Techniques and Designing for Performance would be two I would recommend in this instance.
 
Cheers
Peter
Regards
Peter Boxall
Managing Director
Black Box Consulting
Xilinx Authorised Training Provider
Live Online Instructor Led Training World-WideView solution in original post

没有“安全”的利用率。
如果使用1％或100％的FPGA，设计可靠地工作。
如果您发现问题，我建议您查看您的设计。
例如，异步设计技术可能会导致毛刺和竞争条件，这些干扰和竞争条件可能在电压/温度范围，工艺和批次变化之间产生间歇性。
即使是不同的实现迭代也可以看到地点和路线不同，因此并不总是看到问题。
设计可能间歇性地工作的原因有很多，但我不认为利用率是一个因素。
您可能希望降低利用率的原因可能包括未来更新，功能添加等，如果您没有空间可能无法实现。
放置和布线也可以实现，因此您的性能（和运行时间）可能会受到影响，因为工具的操作空间要小得多，并且必须开始将越来越多的无关逻辑映射到切片或MAP /放置不太理想的东西。
这就是为什么人们倾向于认为设备利用率低于80％但是它的手指在空中并且取决于设备尺寸，留下20％未使用的MAP / PAR灵活性可能是小的或大的。
控制集的数量也可能意味着必须使用更多的设备。
合成是对利用率的估计，性能也是如此。
MAP结果将为您提供可靠的利用率数据。
我不认为在PAR中有任何进一步的优化可以改变这个数字，虽然PAR可能会使用一些LUTS等来实现路由？
其他人可能会证实这一点。
或者，为了安全起见，请使用PAR结果。
我会非常有信心使用MAP进行利用。
syntheis（和MAP）中的不同选项可能会改变切片计数。
优化选项可能是最好的例子。
您可以告诉工具以利用成本优化速度，您可以告诉工具推断某些功能的某些嵌入式块。
即，使用Block RAM而不是分布式RAM，在DSP48切片中构建多路复用器而不是切片，FSM优化等。使用这些选项来尝试达到优化和性能目标是很常见的。
有关这些科目的更多信息可以参加正式的Xilinx培训课程。
设计技巧和技巧以及性能设计将是我在这个例子中推荐的两个。
干杯
彼得
RegardsPeter BoxallManaging DirectorBlack Box ConsultingXilinx授权培训ProviderLive在线讲师带领全球培训



以下为原文

There is no 'safe' utilisation number. The design shoukd work reliably if 1% or 100% of the FPGA is utilised. If you are finding problems, I would recommend looking into your design. For example, asyncronous design techniques can cause glitches and race conditions which can be intermittent across voltage/temperature ranges, process and lot variations. Even a different implementation iteration can see the place and route differ and therefore not always see a problem. There are many reasons why a design might work intermittently but I would not expect the utilisation % to be a factor.
 
Reasons why you may want to reduce your utilisation can include future updates, feature additions etc which might not be possible if you have no space. Place and routing can also be effected and hence your perfomance (and run times) may take a hit as the tools have much less room for manuever and has to start mapping more and more unrelated logic into slices or MAP/Place things less optimal. This is why people tend to consider a device at <80% utilisation but its a finger in the air and depending on device size, leaving 20% unused for MAP/PAR flexibility can be a small or large amount.
 
The amount of control sets might also mean more of the device has to be unused.
 
Synthesis is an estimation of utilisation, as is the performance. The MAP result will give you confident figures of utilisation. I dont think there is any further optimisation done in PAR which can change this figure, although PAR might use up some LUTS etc for route-thru's perhaps? Someone else might be able to confirm this. Or, to be safe, use PAR results. I would be pretty confident using MAP for utilisation though.
 
Different options in syntheis (and MAP) can vary your slice count. Optimisation options are probably the best example of this. You can tell the tools to optimise for speed at the cost of utilisation, you may tell the tools to infer certain embedded blocks for certain features. ie, use Block RAM instead of distributed RAM, build a mux in a DSP48 slice instead of slices, FSM optimisation, etc. It is very common to play with these options to try and reach your optimisation and performance goals.
 
Futher information of these subjects can be found from attending formal Xilinx training courses. Design Tips and Techniques and Designing for Performance would be two I would recommend in this instance.
 
Cheers
Peter
Regards
Peter Boxall
Managing Director
Black Box Consulting
Xilinx Authorised Training Provider
Live Online Instructor Led Training World-Wide