FPGA的外部时钟周期性地打开和关闭

您不必使用DCM。
FPGA内部的逻辑是完全静态的，所以
只要你想要FPGA，就应该没有问题
在时钟停止时什么都不做。
数据设置/保持时间窗口
使用DCM时要好一些，但在40 MHz时你应该没问题
使用没有DCM的时钟。
确保您的时钟转到全局时钟输入
或者“GC”（具有全局时钟功能）引脚，因为它在较新的部件中被调用。
这些针脚
有一个非常短的专用路由到一个全局时钟缓冲区。
延迟内置于
I / O触发器（引脚和D输入之间）确保您没有
积极的保持时间要求。
对于您的应用程序，我会选择该部分
仅基于您的I / O要求。
几乎任何部分都应足以满足
时机并保持你的设计尺寸。
您可能会发现您的引脚要求
强迫您使用比您需要的更大的部件。
在这种情况下
您可以考虑将设计分成两个较小的部分以节省资金。
HTH，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

You don't have to use the DCM.  The logic inside the FPGA is completely static, so
there should be no problem stopping the clock as long as you want the FPGA to
do absolutely nothing while the clock is stopped.  Data setup/hold time windows
are a bit better when using a DCM, but at 40 MHz you should have no problem
using a clock without a DCM.  Make sure your clock goes to a global clock input
or "GC" (global clock capable) pin as it is called in the newer parts.  These pins
have a very short dedicated route to a global clock buffer.  Delays built into the
I/O flip-flops (between the pin and the D input) ensure you don't have a
positive hold time requirement.   For your application I would select the part
based on your I/O requirements only.  Almost any part should be adequate to meet
the timing and hold your design size.  You may find that your pin requirements
force you to use a part that is significantly larger than you need.  In that case
you might consider breaking the design into two smaller parts to save money.
 
HTH,
Gabor
-- GaborView solution in original post

您不必使用DCM。
FPGA内部的逻辑是完全静态的，所以
只要你想要FPGA，就应该没有问题
在时钟停止时什么都不做。
数据设置/保持时间窗口
使用DCM时要好一些，但在40 MHz时你应该没问题
使用没有DCM的时钟。
确保您的时钟转到全局时钟输入
或者“GC”（具有全局时钟功能）引脚，因为它在较新的部件中被调用。
这些针脚
有一个非常短的专用路由到一个全局时钟缓冲区。
延迟内置于
I / O触发器（引脚和D输入之间）确保您没有
积极的保持时间要求。
对于您的应用程序，我会选择该部分
仅基于您的I / O要求。
几乎任何部分都应足以满足
时机并保持你的设计尺寸。
您可能会发现您的引脚要求
强迫您使用比您需要的更大的部件。
在这种情况下
您可以考虑将设计分成两个较小的部分以节省资金。
HTH，
的Gabor
-  Gabor



以下为原文

You don't have to use the DCM.  The logic inside the FPGA is completely static, so
there should be no problem stopping the clock as long as you want the FPGA to
do absolutely nothing while the clock is stopped.  Data setup/hold time windows
are a bit better when using a DCM, but at 40 MHz you should have no problem
using a clock without a DCM.  Make sure your clock goes to a global clock input
or "GC" (global clock capable) pin as it is called in the newer parts.  These pins
have a very short dedicated route to a global clock buffer.  Delays built into the
I/O flip-flops (between the pin and the D input) ensure you don't have a
positive hold time requirement.   For your application I would select the part
based on your I/O requirements only.  Almost any part should be adequate to meet
the timing and hold your design size.  You may find that your pin requirements
force you to use a part that is significantly larger than you need.  In that case
you might consider breaking the design into two smaller parts to save money.
 
HTH,
Gabor
-- Gabor

感谢您的回复，我推进了您的建议..但是因为我是关于时钟的话题;
我想知道是否有人知道如果我需要一个时钟来配置FPGA。
我选择了Xilinx Spartan 3AN，因为它具有用于FPGA配置的内部闪存（不需要外部PROM来保持配置），我是否需要在上电序列期间提供时钟来配置Spartan 3AN FPGA？



以下为原文

Thanks for the reply, I'm moving forward with your recommendation.. but since I'm on the topic of clock; I was wondering if anyone knows that if I need a clock to configure the FPGA. I chose the Xilinx Spartan 3AN since it has internal Flash for FPGA configuration (no external PROM needed to hold configuration), will I need to provide a clock during the power on sequence to configure the Spartan 3AN FPGA?
 
 
 

所有Xilinx FPGA都具有专门用于配置的内部时钟振荡器。
对于
具有外部配置PROM的器件，这将在CCLK引脚上驱动。
对于Spartan 3AN，时钟将在自身的内部包装
从嵌入式闪存配置，但我相信它也可以编程
与其他Spartan 3A部件一样的外部PROM。
无论如何你不需要
用于“主”配置模式的任何板载时钟，或用于加载
通过JTAG实现FPGA或嵌入式闪存。
-  Gabor



以下为原文

All Xilinx FPGA's have internal clock oscillators specifically for configuration.  For
parts with external configuration PROM, this would be driven on the CCLK pin.
For the Spartan 3AN, the clock would be internal to the package during self-
config from the embedded flash, but I believe it can also be programmed from
an external PROM like other Spartan 3A parts.  In any case you don't need
any on-board clock for the "master" configuration modes, or for loading
the FPGA or embedded flash via JTAG.
-- Gabor