乘数码得到res的“00000000”输出

我在下面有这个代码，我无法确定我是否在我的端口图上做了正确的事情。
我得到的是我的res的“00000000”输出。
我使用的组件正常运行。
请帮我修复我的代码。
谢谢。
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL; ----如果在此代码中实例化----任何Xilinx原语，则取消注释以下库声明.-- library UNISIM
;  - 使用UNISIM.VComponents.all;实体乘数为Port（clk：在STD_LOGIC中; rst：在STD_LOGIC中; en：在STD_LOGIC中; opA：在STD_LOGIC_VECTOR中（3 downto 0）; opB：在STD_LOGIC_VECTOR中（3 downto 0）;
res：out STD_LOGIC_VECTOR（7 downto 0）; done：out STD_LOGIC）; end multiplier;架构乘数的行为号码：STD_LOGIC_VECTOR（3 downto 0）：=“0001”;信号tempA：STD_LOGIC_VECTOR（3 downto 0）;信号tempB
：STD_LOGIC_VECTOR（3 downto 0）;信号tempC：STD_LOGIC_VECTOR（3 downto 0）;信号tempD：STD_LOGIC_VECTOR（3 downto 0）;信号tempE：STD_LOGIC; COMPONENT clahead_addr PORT（clk：IN std_logic; operandA：IN std_logic_vector（3 downto 0）
）; operandB：IN std_logic_vector（3 downto 0）; carry_in：IN std_logic; sum：OUT std_logic_vector（3 downto 0）;
carry_out：OUT std_logic）;
结束组成部分;
COMPONENT移位器PORT（clk：IN std_logic; rst：IN std_logic; op1：IN std_logic_vector（3 downto 0）; op2：IN std_logic_vector（3 downto 0）; din：IN std_logic; out1：OUT std_logic_vector（3 downto 0）; out2
：OUT std_logic_vector（3 downto 0））;
结束组成部分;
--Inputs SIGNAL operand1：std_logic_vector（3 downto 0）;
SIGNAL operand2：std_logic_vector（3 downto 0）;
SIGNAL done1：std_logic;
- 输出SIGNAL sum：std_logic_vector（3 downto 0）;
SIGNAL carry_out1：std_logic;
SIGNAL carry_out2：std_logic;
SIGNAL outA：std_logic_vector（3 downto 0）;
SIGNAL outB：std_logic_vector（3 downto 0）;
begin uut1：clahead_addr PORT MAP（clk => clk，operandA => operand1，operandB => operand2，carry_in =>'0'，sum => sum，carry_out => carry_out1）;
uut2：移位器端口映射（clk => clk，rst => rst，op1 => sum，op2 => tempB，out1 => outA，out2 => outB，din => carry_out1）;进程（rst，en，clk，
tempB，number，tempA，outA，outB）如果rst ='1'则开始，然后res operand1 operand2 tempA tempB tempC tempD tempE elsif en ='1'然后tempA tempB elsif clk'event和clk ='1'然后如果tempB（0）
）='1'和数字=“0001”然后操作数2操作数1 tempB数字elsif tempB（0）='1'和数字=“0010”然后操作数2操作数1 tempB数字elsif tempB（0）='1'和数字=“0100
“然后operand2 operand1 tempB number elsif tempB（0）='1'和number =”1000“then operand2 operand1 tempB number elsif tempB（0）='0'且number =”0001“then operand2 operand1 tempB number elsif tempB（0
）='0'和数字=“0010”然后操作数2操作数1 tempB数字elsif tempB（0）='0'和数字=“0100”然后操作数2操作数1 tempB数字elsif tempB（0）='0'和数字=“1000
“然后操作数2操作数1 tempB数字elsif数=”0000“然后res（7）res（3）数字结束if;
万一;
结束过程;结束行为;
消息adrialex于08-09-2009 12:38 AM编辑



以下为原文

I have this code below and i can't determine whether or not i did the right thing on my portmaps. All i get is a "00000000" output for my res. The components that I used are functioning right. Pls help me fix my code. Thank You.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           en : in  STD_LOGIC;
           opA : in  STD_LOGIC_VECTOR (3 downto 0);
           opB : in  STD_LOGIC_VECTOR (3 downto 0);
           res : out  STD_LOGIC_VECTOR (7 downto 0);
           done : out  STD_LOGIC);
end multiplier;

architecture Behavioral of multiplier is
signal number : STD_LOGIC_VECTOR (3 downto 0) := "0001";
signal tempA : STD_LOGIC_VECTOR (3 downto 0);
signal tempB : STD_LOGIC_VECTOR (3 downto 0);
signal tempC : STD_LOGIC_VECTOR (3 downto 0);
signal tempD : STD_LOGIC_VECTOR (3 downto 0);
signal tempE : STD_LOGIC;

COMPONENT clahead_addr
    PORT(
        clk : IN std_logic;
        operandA : IN std_logic_vector(3 downto 0);
        operandB : IN std_logic_vector(3 downto 0);
        carry_in : IN std_logic;         
        sum : OUT std_logic_vector(3 downto 0);
        carry_out : OUT std_logic
        );
    END COMPONENT;
   
    COMPONENT shifter
    PORT(
        clk : IN std_logic;
        rst : IN std_logic;
        op1 : IN std_logic_vector(3 downto 0);
        op2 : IN std_logic_vector(3 downto 0);
        din : IN std_logic;         
        out1 : OUT std_logic_vector(3 downto 0);
        out2 : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
    --Inputs
    SIGNAL operand1 :  std_logic_vector(3 downto 0);
    SIGNAL operand2 :  std_logic_vector(3 downto 0);
    SIGNAL done1 : std_logic;
   

    --Outputs
    SIGNAL sum :  std_logic_vector(3 downto 0);
    SIGNAL carry_out1 :  std_logic;
    SIGNAL carry_out2 :  std_logic;
    SIGNAL outA :  std_logic_vector(3 downto 0);
   SIGNAL outB :  std_logic_vector(3 downto 0);
   
begin

    uut1: clahead_addr PORT MAP(
        clk => clk,
        operandA => operand1,
        operandB => operand2,
        carry_in => '0',
        sum => sum,
        carry_out => carry_out1
    );
   
    uut2: shifter PORT MAP(
        clk => clk,
        rst => rst,
        op1 => sum,
        op2 => tempB,
        out1 => outA,
        out2 => outB,
        din => carry_out1
    );
process (rst, en, clk, tempB, number, tempA, outA, outB)
begin
    if rst = '1' then
        res <= "00000000";
        operand1 <= "0000";
        operand2 <= "0000";
        tempA <= "0000";
        tempB <= "0000";
        tempC <= "0000";
        tempD <= "0000";
        tempE <= '0';
    elsif en = '1' then
        tempA <= opA;
        tempB <= opB;
    elsif clk'event and clk = '1' then
        if tempB(0) = '1' and number = "0001" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0010";
        elsif tempB(0) = '1' and number = "0010" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0100";
        elsif tempB(0) = '1' and number = "0100" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "1000";
        elsif tempB(0) = '1' and number = "1000" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0000";
            
        elsif tempB(0) = '0' and number = "0001" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0010";
        elsif tempB(0) = '0' and number = "0010" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0100";
        elsif tempB(0) = '0' and number = "0100" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "1000";
        elsif tempB(0) = '0' and number = "1000" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0000";
            
        elsif number = "0000" then
            res(7) <= operand1(3); res(6) <= operand1(2); res(5) <= operand1(1); res(4) <= operand1(0);
            res(3) <= tempB(3); res(2) <= tempB(2); res(1) <= tempB(1); res(0) <= tempB(0);
            number <= "0001";
        end if;
        
    end if;   
   
end process;

end Behavioral;
Message Edited by adrialex on  08-09-2009 12:38 AM