无法正确控制时钟

将200 MHz驱动至3.3V引脚会让您长期悲伤。
这是一个非常高的
频率，你最好小心信号终止，即阻抗控制。
如果你不知道这是什么，做一些学习 - 你需要了解这一点
以200 MHz的速率！
您是否为您的时钟引脚设置了SLEW = FAST选项
时钟输出引脚？
您的时钟输出引脚是否终止于信号线的末端？
或者你正在使用系列
终止？
你有没有想过这个？
在200 MHz时，您是否考虑过如何为数据设置/保持时间提供正确的数据
DAC数据？
您可以查看BUFG与IBUFG的其他线程，但基本上两者都是时钟缓冲区，但是
其中一个用于输入引脚，另一个用于将内部信号路由到全局时钟线。
祝你好运！
约翰普罗塞纳



以下为原文

Driving 200 MHz onto a 3.3V pin will give you long term grief.  This is a pretty high
frequency and you better be very careful about signal termination, ie, impedance control.
 
If you don't know what this is, do some studying - you're going to need to understand this
at the 200 MHz rates!
 
Do you have the SLEW=FAST option set for your clock pin in your constraints for the
clock output pin?
 
Is your clock output pin terminated at the end of the signal line?  Or are you using series
termination?  Have you thought about this?
 
At 200 MHz, have you thought about how you provide the proper data setup/hold time for
the DAC data?
 
 
You can look at other threads for BUFG vs IBUFG, but basically both are clock buffers, but
one of them is for input pins, the other routes an internal signal to a global clock line.
 
Good luck!
 
John Providenza

z10n0101写道：大家好，
我对FPGA世界还很陌生，目前我需要从FPGA板驱动DAC电路，
但我卡住了因为我无法正确控制时钟（200MHz）： 
我最近学会了如何使用DCM从100MHz时钟（系统时钟）生成该频率， 
然后我用示波器检查结果，频率是正确的，但它是正弦波（而不是方波） 
当该端口应该给出0-3.3V时，具有高直流偏移（大约1v）和小振幅（0.2V pk-pk）。
我也试过较低的频率，我观察到类似的结果，但不那么戏剧性。
你的'范围的模拟带宽是多少？
你的探头的模拟带宽是多少？
你在什么时候连接'示波器探头接地？
（提示：3英寸长的地线会导致错误！）
我想知道这是否正常，是否可以通过软件解决
（如果不是必需的话，我不想制作额外的模拟电路）
它可能是一个测量工件。
往上看。
PS：有没有人能够很好地理解befwen bufg和ibufg的差异？
干杯。
数据表和系列用户指南有完美的解释。
我邀请你阅读它们。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

z10n0101 wrote:
Hello all,
 
I am fairly new to the FPGA world, at the moment I need to drive a DAC circuit from a FPGA board,
but Im stuck because I cannot correctly control the clock (200MHz):
 
I recently  learnt how to generate that frequency from a 100MHz clock (the system clock) by using a DCM,
then I checked the result with an oscilloscope and the frequency is correct but it is sine wave (instead of square)
with a high dc offset (around 1v) and a small amplitude (0.2V pk-pk ) when that port is supposed to give 0-3.3V.
I also tried with lower frequencies and I observed similar results but less dramatic. 
 

What is your 'scope's analog bandwidth?
 
What is your probe's analog bandwidth?
 
To what point are you connecting the 'scope probe ground? (Hint: the 3"-long ground wire will induce errors!)

 
 
I would like to know if this is somewhat normal and if it can be solved via software
(I wouldnt like to make an extra analog circuit, if it is not necesssary)
 

 It's probably a measurement artifact. See above.
 

 
PS: does anybody has a good reference to understand the differences beetwen bufg and ibufg?
 
Cheers. 
 

 
The data sheets and family user guides have perfectly excellent explanations. I invite you to read them.
 
-a
----------------------------Yes, I do this for a living.

John已经指出了一些基本和好的观点，在高速CLK播放时必须经常检查。
当你将每一个Clk连接到FPGA的CLK引脚时 - 你会在Clk引脚之后连接一个IBUFG。
它是IOB的一部分。
关于你与CRO的问题 - 我想提出一个非常基本的观点，很多时候设计师从软件背景中错过了。
CRO的采样频率对于显示波形也起着重要作用。
假设一个人使用100MHz CRO检查50MHz方波，他将在屏幕上得到一个三角波形。
同样，如果您使用500MHz CRO进行200MHz方波，您将在屏幕上看到像波形一样的波形。此外，探头的电容起着重要作用。
您应该确认时间段是您所期望的。
而且过冲和下冲应该在限度内。
如果是，您可以连接设备 - 至少它不会损坏您的设备。
BUFG需要增加扇出。
假设您应该将Bufg连接到DCM的输出，然后从您的设计中获取bufg的o / p中的clk o / p。
有关详细信息，请查看以下链接 -
http://www.xilinx.com/itp/xilinx8/books/data/docs/lib/lib0061_25.html
http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0230_198.html
山塔努
Shantanu Sarkarhttp：//www.linkedin.com/pub/shantanu-sarkar/0/33a/335



以下为原文

John has pointed out some basic andd good points, which one has to always check while playing with high speed CLK.
When ever you are connecting a Clk to a CLK pin of the FPGA - you shld connect a IBUFG after the Clk Pin. Its a part of IOB.
 
Regarding your problem with CRO - I'll like to bring one a very basic point, which many times a designer from software background miss. The sampling freq of the CRO also plays a big role for displaying a waveform. Say if one is using 100MHz CRO to check 50MHz Square wave, he will get a triangular waveform in the screen. Similarly if you are using a 500MHz CRO for 200MHz Square wave, you will get a sine wave like waveform in the screen. Also the capacitance of the Probe plays a big role.
 
You should make confirm the time period is what you expect. And the overshoot and Undershoot should be within limits. If it is you can connect the device - atleast it will not damage your device.
 
 
BUFG is required to increase the fan out. Say you should connect the Bufg to the output of DCM and then should take the clk o/p from the o/p of bufg for your design. For details check out the following links -
 
http://www.xilinx.com/itp/xilinx8/books/data/docs/lib/lib0061_25.html
http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0230_198.html
 
Shantanu
 
 
 
Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335