Xilinx 14.7使用zybo板出现错误

SAYO @ 14，
您是否拥有ISE的有效许可证？
你可以共享运行Xinfo System Checker后应该生成的xinfo.txt文件吗？
同时查看类似的论坛帖子：
https://forums.xilinx.com/t5/Installation-and-Licensing/ISE-ERROR-Security-9c-No-ISE-nor-WebPack-feature-was-available/td-p/568756
--Syed
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在原帖中查看解决方案



以下为原文

sayo@14,
 
Do you have a valid license for ISE?
Can you share the xinfo.txt file which should be generated after running Xinfo System Checker
 

 
Also check the similar forum thread:
https://forums.xilinx.com/t5/Installation-and-Licensing/ISE-ERROR-Security-9c-No-ISE-nor-WebPack-feature-was-available/td-p/568756
 
--Syed
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嗨sayo @ 14
您似乎没有相应的许可证和/或您所拥有的许可证不支持您正在使用的设备。
请在此附上许可文件。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi sayo@14
 
Looks like you dont have the corresponding license and/or the license you have doesnt support the device you are working with.
Please attach the license file here.
Thanks,Vijay
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Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
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SAYO @ 14，
您是否拥有ISE的有效许可证？
你可以共享运行Xinfo System Checker后应该生成的xinfo.txt文件吗？
同时查看类似的论坛帖子：
https://forums.xilinx.com/t5/Installation-and-Licensing/ISE-ERROR-Security-9c-No-ISE-nor-WebPack-feature-was-available/td-p/568756
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

sayo@14,
 
Do you have a valid license for ISE?
Can you share the xinfo.txt file which should be generated after running Xinfo System Checker
 

 
Also check the similar forum thread:
https://forums.xilinx.com/t5/Installation-and-Licensing/ISE-ERROR-Security-9c-No-ISE-nor-WebPack-feature-was-available/td-p/568756
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

喜
Pinfo的xinfo.txt和license.lic文件......
问候，
小夜
xinfo 1 KB
xinfo 1 KB
license.lic 21 KB



以下为原文

hi,
PFA of xinfo.txt and license.lic file...
 
 
 
Regards,
Sayo
            xinfo ‏1 KB                xinfo ‏1 KB                license.lic ‏21 KB

plzzzzzzzzz回复........我要做的就是解决这个问题..



以下为原文

plzzzzzzzzz reply........what I have to do to solve this problem..

我有附图...



以下为原文

I have attached image...

Plzzz回复..我要做什么........问候，sayali b



以下为原文

Plzzz reply.. what I have to do........

regards,
sayali b

我必须做些什么来解决这个问题。
我再次附上了xinfo和许可证..
xinfo.txt 58 KB
license.lic 21 KB



以下为原文

what I have to do to solve this problem. I have attached xinfo and license again..
            xinfo.txt ‏58 KB                license.lic ‏21 KB

嗨sayo @ 14
看起来你没有ISE许可证。
我只能看到IP许可证但没有ISE许可证。
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi sayo@14
Looks like you dont have ISE license. All I could see are the IP licensens but no ISE license.
 
Thanks,Vijay
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非常感谢你vijay ......
现在，我尝试了这个xilinx.lic ....
Xilinx.lic 1 KB
Xilinx.lic 1 KB



以下为原文

Thank u so much vijay......
Now, I tried with this xilinx.lic....
            Xilinx.lic ‏1 KB                Xilinx.lic ‏1 KB   

嗨sayo @ 14
那么使用此许可证的运行状态如何？
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi sayo@14
So what is the status of your run with this license?
Thanks,Vijay
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实际上这个问题已经用xilinx.lic解决了，但现在我正在解决新的问题
错误：Pack：1107  -  Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容。
错误：Pack：1107  -  Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容。
当我执行.ucf文件时，我发现了这些错误
我的.ucf文件格式为ZYBO（XC7Z010，CLG400ACX1437）FPGA板
NET“clk”loc = E7; NET“updown”loc = G15; NET“Q [0]”loc = M14; NET“Q [1]”loc = M15; NET“Q [2]”loc = G14; NET
“Q [3]”loc = D18; NET“reset”loc = B4;
和VERILOG代码
模块Count_code（Q，clk，updown，reset）; // ----------输出端口--------------输出[3：0] Q; //
------------输入端口--------------输入clk，updown，reset; // ------------内部
变量-------- reg [3：0] temp;
reg clk_div;
localparam constantNumber = 25000000;
reg [31：0]计数;总是@（posedge（clk），negedge（重置））如果（reset == 1'b0）则开始计数if if（count == constantNumber  -  1）count count count endalways @（posedge（
clk），negedge（reset））if if（reset == 1'b0）clk_div else if（count == constantNumber  -  1）clk_div else clk_div endassign Q = temp; always @（posedge clk_div or negedge reset）beginif（reset =
= 1'b0）temp else if（updown == 1'b1）temp else temp end endmodule
我必须做些什么来消除这些错误....



以下为原文

Actually that problem solved with xilinx.lic but now I am fetching new problem that is
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.
 
When I execute .ucf file I found these errors
 
My .ucf file format for ZYBO (XC7Z010, CLG400ACX1437) FPGA BOARD
NET "clk" loc = E7;
NET "updown" loc = G15;
NET "Q[0]" loc = M14;
NET "Q[1]" loc = M15;
NET "Q[2]" loc = G14;
NET "Q[3]" loc = D18;
NET "reset" loc = B4;
 
AND VERILOG CODE
module Count_code(Q ,clk , updown, reset );
//----------Output Ports--------------
    output [3:0] Q;
//------------Input Ports--------------
     input  clk,updown, reset;
//------------Internal Variables--------
    reg [3:0] temp;
     reg clk_div;
     localparam constantNumber = 25000000;
    reg [31:0] count;
always @ (posedge(clk), negedge(reset))
begin
    if (reset == 1'b0)
        count <= 32'b0;
    else if (count == constantNumber - 1)
        count <= 32'b0;
    else
        count <= count + 1'b1;
end
always @ (posedge(clk), negedge(reset))
begin
    if (reset == 1'b0)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end
assign Q = temp;
always @(posedge clk_div or negedge reset)
begin

 if (reset == 1'b0)
  temp <= 4'b0000;
  else if (updown== 1'b1)
  temp <= temp - 1'b1;
  else
  temp <= temp + 1'b1;
 end  
endmodule
 
What I have to do to remove these errors....
 
 
 

嗨sayo @ 14
在标题问题得到解决后，请通过标记解决方案来关闭该线程，并为您看到的Pack问题创建一个新线程。
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi sayo@14
As the title issue is resolved, please close the thread by marking the solution and create a new thread for the Pack issue you are seeing.
Thanks,Vijay
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Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
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