购买ISE 13.1的成本是多少

WebPACK是免费的（如在啤酒中），类似于Logic Edition但在设备支持方面有限，缺少Chipscope，并且具有ISIM Lite：
http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm
http://www.xilinx.com/publications/matrix/Software_matrix.pdf
http://www.xilinx.com/products/design_tools/logic_design/verification/ise_simulator_faq.htm
您可以在此处查看版本部件#s并链接到Avnet以进行定价：
http://www.xilinx.com/onlinestore/design_resources.htm
常见的许可问题：
http://www.xilinx.com/tools/faq.htm（许可，下载和安装常见问题解答）
迁移设计的难度将取决于现有V4设计的性质，包括资源需求，资源的使用方式（推断与实例化和核心网表相比）等。行为RTL比在家庭之间改变的收发器更容易
（GT11  - > GTP / GTX）但架构向导可以帮助后者。
您可能也希望重新生成任何核心。
BT



以下为原文

WebPACK is free (as in beer), similar to Logic Edition but limited in device support, lacks Chipscope, and has ISIM Lite:
http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm
http://www.xilinx.com/publications/matrix/Software_matrix.pdf
http://www.xilinx.com/products/design_tools/logic_design/verification/ise_simulator_faq.htm

 
You can see the Edition part #s and link to Avnet for pricing here:
http://www.xilinx.com/onlinestore/design_resources.htm
 
Common licensing questions:
http://www.xilinx.com/tools/faq.htm (Licensing, Download & Installation FAQs)
 
The difficulty in migrating the design will depend on the nature of the existing V4 design, including resource needs, how the resources are used (inferred vs instantiated vs core netlists), etc. Behavioral RTL is much easier than something like transceiver that changed between families (GT11 -> GTP/GTX) but the architecture wizards can help with the latter.
 
You will likely want to regenerate any cores as well.
 
bt

如何使用资源（推断vs实例化与核心网表）
--->请解释上面这一行..这有什么不同......因为生成的逻辑总是相同的。



以下为原文

how the resources are used (inferred vs instantiated vs core netlists)
---> Kindly explain the above line.. how does this makes a difference.. as the logic generated would always be same.

一些简单的例子（对于V4  - > V5的情况）。
- 一般面料是不同的。
V4是每片经典的2 LUT4 + 2FF。
V4每片4个LUT6 + 4个FF。
如果您重新合成，它应该导致更有效的使用和更少的逻辑级别。
如果您只使用V4网表而不重新生成，则效率不高：
http://www.xilinx.com/support/documentation/white_papers/wp248.pdf(Virtex-5 FPGA的重定向指南）
-V4使用DSP48，而V5使用DSP48E。
有些操作支持推理（然后有些需要属性），而其他操作则要求你实例化原语。
例如，DSP48宏可帮助您构建时分多路复用逻辑，如果滤波器的速率低于DSP片可以运行的话，这非常有用。
也适用于FIR编译器等内核
-V4使用RAMB16，而V5使用可以分解为2的RAMB36。某些操作支持推理，而其他操作需要实例化。
无法推断出一些原语：
- 以太网MAC基元略有不同（V4FX  - > V5LXT / SXT / FXT / TXT）
- 收发器不同（V4FX  - > V5LXT / SXT GTP或V5FXT / TXT GTX）
-  PPC不同（V4FX上405，V5FXT上440）
-V4使用IDELAY但V5使用IODELAY
-V4具有DCM＆amp;
PMCD，而V5的CMT有DCM＆amp;
PLL。
虽然映射器可以在某些情况下重新定位PMCD，但最好使用时钟Arch Wiz重新生成它
许多核心在需要时实例化原语，而其他核心则推断它们。
只要您重新生成核心并且在系列之间支持，差异就很大程度上是透明的。
但我的观点是不要盲目重用它们。
也期待完全相同的逻辑＆amp;
推理和实例化之间的表现是不现实的 - 特别是当您考虑不同综合工具的效果以及不同用户的编码风格时 - 有时这很重要。
您也可以使用从未移植到V5的第三方网表，但您没有源，他们也没有为V4提供此功能。
现有的网表可能会或可能不会起作用，具体取决于其中一些细节。
或者可能会工作，但不能尽可能高效。
我的另一点是并非所有V4设计都透明地映射到V5而无需用户努力。
“总是一样的”依赖于对这些细节的许多假设......;）



以下为原文

A few quick examples (for the case of V4 ->V5).
 
-the general fabric is different. V4 is the classical 2 LUT4 + 2FFs per slice. V4 is 4 LUT6 + 4 FFs per slice. If you resynthesize, it should result in more efficient usage with less logic levels. If you just use a V4 netlist without regenerating, it will not be as efficient:
http://www.xilinx.com/support/documentation/white_papers/wp248.pdf (Retargeting Guidelines for Virtex-5 FPGAs)
 
-V4 uses a DSP48 while V5 uses a DSP48E. Several of the operations are supported for inferrence (and then some require an attribute) while others require you to instantiate the primitive. For example, the DSP48 macro helps you build the logic to time division multiplex these, which is useful if you filter rates are lower than the DSP slices can run. Also applicable to cores like the FIR compiler
 
-V4 uses a RAMB16 while V5 uses a RAMB36 that can be fractured into 2. Some operations are supported for inferrence while others require instantiation.

Some primitives can't be inferred:
-the Ethernet MAC primitives are slightly different (V4FX -> V5LXT/SXT/FXT/TXT)
-the transceivers are different (V4FX -> V5LXT/SXT GTP or V5FXT/TXT GTX)
-the PPCs are different (405 on V4FX, 440 on V5FXT)
-V4 uses an IDELAY but V5 uses an IODELAY
-V4 has a DCM & PMCD while V5's CMT has a DCM & PLL. While the mapper can retarget the PMCD in some cases, you are better off regenerating it with the clocking Arch Wiz
 
Many of the cores instantiate primitives where needed while others infer them. The difference is largely transparent as long as you regenerate the core and it is supported between families. But my point was to not blindy reuse them.
 
Also expecting the exact same logic & performance between inferrence and instantiation is not realistic - especially when you consider the effects of different synthesis tools as well as different users' coding styles - sometimes this is important.
 
You could also be using a 3rd party netlist that was never ported to V5 and you don't have source and they don't offer this for V4. The existing netlist might or might not work depending on some of these details. Or might work but not be as efficient as it could be.
 
My other point was not all V4 designs transparently map to V5 with no user effort.
 
"would always be the same" relies on a lot of assumptions with respect to some of these details... ;)