如何将字节宽的接口添加到UDB Designer组件？

我试图用UDB编辑器创建一个16位加法器。首先，这是可能的吗？看来，如果我想要一个带有48个“引脚”的设备，我可能没有足够的寄存器来处理两个输入字和一个输出字。
我想背景可能会有帮助。我试图建立DMA以允许写入（至少），并且理想地也可以从SRAM上的4K阵列上读取PSoC 5（也可能是PSoC 4）。我有一个16位地址总线实现两套8 GPIO引脚。来自外部总线的访问是随机的，一次一个字节。R/W引脚指示数据流的方向，并且还有另外8个引脚用于D0—D7。目前在SRAM中写入单个UIT8的效果良好，但不能基于GPIO地址来处理多个位置。
我认为我需要的是这个加法器，所以我可以在启动时把它加载到数组的基地址，并将它添加到来自地址总线的较低12位的数组中的偏移量。
我一直在寻找索引的DMA解决方案，但是关于它的文档非常稀少，我仍然看不出它会怎么做我需要的。据我所知，索引DMA工作，如果你可以从其他地方获得绝对目的地地址。我可以得到相对偏移，但不是绝对地址…因此需要（我想）加法器。我确实看到Keil编译器允许在SRAM中进行一些明确的对象定位，但我使用的是GCC。
所以，我目前在UDB编辑器中的目标是这个加法器。很容易看到如何设置一些指令和状态机状态来从D0加载A0，然后将A0添加到D1，并从ALUUT中获得结果。我无法看到的是如何正确地在组件中使用字节或字宽的接口，这样我就可以将它们连接到我的PIN。UDB设计器允许我添加单针/位输入，它还允许我添加设计范围变量（但设计范围变量似乎几乎没有文件……）什么是注册与组合？允许哪些表达式？想想看，我真的只需要12个“PIN”的偏移地址从我的GPIO引脚。我可以在固件/软件中读写。
总而言之，这就是我认为我需要的：
---在解决方案中---
1。从GPIO引脚连接AD0A12到加法器组件…也可以连接CS或其他启用信号或时钟
2。配置DMA使用来自加法器输出的地址作为目的地
---跑步时---
1。创建4K UIT8阵列
2。将数组起始地址的Lo16设置为加法器
三。（当一个新的地址可用时，加法器将提供一个计算的绝对对应地址到4K数组中，以便DMA读写请求可以发出或存储正确的字节位置）。
我一直在阅读UDB编辑器上的AN。我还没有找到我需要的东西。我得到的印象是，我需要先使用FIFO寄存器来加载D0和D1，但我仍然不知道如何从硬件输入加载F0和F1。我也把控制寄存器丢到了设计中，但是我看不出如何把它绑定到任何东西上。
最坏的情况是，我可以通过中断将一个DMA接收到的字节复制到缓冲区中的正确位置，或者，我可以创建一个中断处理程序，在DMA完成后将每个写入的字节复制到数组中的正确位置，但这是一个非常麻烦的问题。我已经知道，在PoSoC 4上，整个CPU驱动的数据读取过程不够快。硬件/固件可寻址的DMA在这里看起来更优雅。
所以，先感谢一些我正在尝试做的指示，或者我应该阅读的文档。
谢谢，保罗



     以下为原文
  I'm trying to create a 16-bit adder using the UDB Editor. First of all, is this even possible? It seems that if I want a device with 48 "pins" I may not have enough registers to handle two words of input and one word of output.

Background might help, I guess. I am trying to set up DMA to allow write (at least), and ideally also read, from a 4K array in SRAM on PSOC 5 (and maybe also PSOC 4). I have a 16-bit address bus implemented in two sets of 8 GPIO pins. The access from the external bus is random, and one byte at a time. A R/W pin indicates the direction of data flow, and there are another 8 pins for D0-D7. This currently works fine for writing to a single uint8 in SRAM, but not for being able to address multiple locations based on the GPIO address.

What I think I need is this adder, so I can load it with the base address of the array at startup, and have it add to that the offset into the array coming from the lower 12 bits of the address bus.

I've been looking for indexed DMA solutions, but the documentation on that is really sparse and I still can't see how it would do what I need. As far as I can tell, indexed DMA works if you can get the absolute destination address from somewhere else. I can get the relative offset, but not the absolute address... thus the need (I think) for an adder. I do see that the Keil compiler allows some explicit object positioning in SRAM, but I'm using gcc.

So, the goal I'm currently working towards in the UDB Editor is this adder. It's pretty easy to see how to set up some instructions and state machine states to load A0 from D0, then add A0 to D1 and have the result available from the ALUout. What I can't see is how to correctly make byte or word wide interfaces available in the component so I can connect them to my pins. UDB Designer allows me to add single pin/bit inputs, and it also allows me to add design-wide variables (but the design-wide variables seem to be almost undocumented... what is registered vs. combinatorial? what kinds of expressions are allowed for them?) Come to think of it, I really only need 12 "pins" for the offset address from my GPIO pins. Everything else I can read and write in firmware/software.

To recap, here's what I think I need:

--- in the solution ---
1. Connect AD0-A12 from GPIO pins to the adder component... maybe also connect CS or some other enable signal or clock
2. Configure DMA to use address from adder output as destination

--- when running ---
1. Create 4K uint8 array
2. Set the LO16 of the array start address into the adder
3. (when a new address is available, the adder will be providing a computed absolute corresponding address into the 4K array so DMA read or write requests can source or store the correct byte location)

I've been reading through the AN's on the UDB Editor. I'm not yet finding what I need. I get the impression that I need to use the FIFO registers to load D0 and D1 first, but I still don't see how to load F0 and F1 from hardware inputs. I also dropped a Control Register into the design, but I can't see how to hook that up to anything.

Worst case, I might be able to make this work with an interrupt to copy a single DMA-received byte to the correct location in the buffer, or, I guess I could create an interrupt handler to copy each written byte into the correct place in the array after DMA is complete, but that's a lot messier and I already know the entire CPU-driven data read process isn't fast enough on PSOC 4. Hardware/firmware addressable DMA seems so much more elegant here.   

So, thanks in advance for some pointers on what I'm trying to do, or towards documentation that I should be reading.

Thanks,
Paul