virtex7中的实现重复

你好
现在，我正在使用virtex-7-2000T。
基本上，有4个NAND PHY，它支持DDR接口。
因此，时序要求有点紧张。
因此，在我们在XDC中设置正确的约束之后，在0326实现时关闭时序。
但是，在0328，我们改变了RTL，而不是NAND PHY设计，VIVADO报告定时故障，大约-3ns。
但是，0326和0328具有完全相同的NAND PHY设计。
以下是带DDR接口的4个子模块。
u_core_top / u_pd_top / u_ncb_top / ndphy_ch_inst [0] .u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho
u_core_top / u_pd_top / u_ncb_top / ndphy_ch_inst [1] .u_ndphy_ch_top_inst.u_ndphy_ch_top
u_core_top / u_pd_top / u_ncb_top / ndphy_ch_inst [2] .u_ndphy_ch_top_inst.u_ndphy_ch_top
u_core_top / u_pd_top / u_ncb_top / ndphy_ch_inst [3] .u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho
我在想是否有任何方法可以直接将0326 NAND_PHY复制到0328设计，包括loc，FF，路径等。我之前尝试过布局，但时机更糟。
我希望当NAND PHY完全相同时，我们可以获得一致的实现。
如果有人能解决我的问题，我们将不胜感激。
谢谢
陈平
2018年3月29日



以下为原文

Hi, there

Now, I am working virtex-7-2000T. Basically, there are 4 NAND PHY, which support DDR interface. So, the timing requirement is a little bit tight. So, after we setup the correct constrains in the XDC, the timing is closed on 0326 implementation. But, on 0328, we change the RTL, not NAND PHY design, VIVADO report timing failure, around -3ns. But, 0326 and 0328 have exact same design for NAND PHY. The following is the 4 sub-module with DDR interface.

u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[0].u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho
u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[1].u_ndphy_ch_top_inst.u_ndphy_ch_top
u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[2].u_ndphy_ch_top_inst.u_ndphy_ch_top
u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[3].u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho

I am thinking whether there is any way for me to copy the 0326 NAND_PHY to 0328 design directly, including loc, FF, route path, etc.  I try floorplan before, but timing is worse. I hope that we can get the consistent implementation when NAND PHY is exactly same.

It is highly appreciated it if someone can solve my problem. thanks

Ping Chen

2018.3.29