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Vivado在布局器中生成错误：ERROR：[DRC 23-20]规则违规（HAUMR-2）意外的mysignal时钟周期 - mysignal时钟周期不正确。
确保在XDC约束文件中正确约束mysignal_clkin和mysignal_clk.mysignal_clk是必需的，但在设计中找不到。 .xdc在约束信号时显示正确： create_clock [list [get_ports {pin_BC27}] [get_ports {pin_BC27}]] -name {mysignal_clkin} -period {10.000} -waveform {0.000 5.000} 16.3及更高版本会发生此错误。 有什么想法吗？ 以上来自于谷歌翻译 以下为原文 Vivado is generating an error in placer: ERROR: [DRC 23-20] Rule violation (HAUMR-2) Unexpected mysignal clock period - mysignal Clock period is incorrect. Make sure that the mysignal_clkin and mysignal_clk are correctly constrained in the XDC constraint files. mysignal_clk is required but not found in the design. The .xdc appears correct in constraining the signal: create_clock [list [get_ports {pin_BC27}] [get_ports {pin_BC27}]] -name {mysignal_clkin} -period {10.000} -waveform {0.000 5.000} This error occurs with 16.3 and later versions. Any ideas on this? 
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5个回答
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你好@ petemar
你能在合成设计上运行report_clocks命令，看看是否报告了名为'mysignal_clkin'的时钟？ 是否有任何与帖子中提到的create_clock约束相关的严重警告？ 你可以共享xdc文件以及synth dcp来进一步调试吗？ 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi @petemar Can you run report_clocks command on the synthesized design and see if the clock named 'mysignal_clkin' is reported? Is there any critical warnings related to create_clock constraint mentioned in the post? Can you share the xdc file as well as the synth dcp to debug this further? Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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没有其他有关时钟的参考，没有关键警告或任何其他内容。
运行report_clocks后，报告为空！ 但.xdc中的约束看起来是正确的。 时钟ReportAttributes P：传播G：生成V：虚拟I：反向时钟周期（ns）波形（ns）属性源========================== ==========================生成时钟====================== ================================================== ================================用户不确定性================ ================================================== ======================================用户抖动========== ========================================== 以上来自于谷歌翻译 以下为原文 There are no other references to the clock in question, no CRITICAL WARNING or anything. After running report_clocks, the report is empty! The constraint in the .xdc looks correct though. Clock Report Attributes P: Propagated G: Generated V: Virtual I: Inverted Clock Period(ns) Waveform(ns) Attributes Sources ==================================================== Generated Clocks ==================================================== ==================================================== User Uncertainty ==================================================== ==================================================== User Jitter ==================================================== |
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你好@ petemar
看起来您的设计流程存在一些问题。 你能否分享一下存档的项目或至少xdc文件来调查这个问题？ 看起来xdc文件也不是由综合定时引擎编译的。 您可以单击源层次结构中的xdc文件。 然后转到文件的属性并确保'USED_IN'属性设置为综合和实现，如下所示： 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi @petemar Looks like there is some issue with your design flow. Can you please share the archived project or atleast xdc file to look into this issue? Looks like the xdc file is not compiled by synthesis timing engine as well. Can you click on the xdc file in the source hierarchy. Then go to properties of the file and make sure the 'USED_IN' property is set to synthesis and implementation as shown: Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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有没有我可以发送.xdc的电子邮件？
我们使用Synplify进行合成，并从该工具生成.xdc。 以上来自于谷歌翻译 以下为原文 Is there an email that I can send the .xdc? We use Synplify for synthesis and the .xdc is generated from that tool. |
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你好@ petemar
请查看您的PM（私信）。 如果您遗漏了任何内容，还可以查看下面链接中的第三方综合工具流程，第5章。 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug896-vivado-ip.pdf 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi @petemar Please see your PM(Private messages). Also have a look at the third party synthesis tool flow in the link below, Chapter 5 if you are missing anything. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug896-vivado-ip.pdf Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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