[问答]

使用Kintex-7 FPGA嵌入式套件实现错误

问答对人有帮助，内容完整，我也想知道答案 0 我做了一堆仿真工作，并且构建正常。它有警告，但没有错误。我的目标硬件是Kintex-7 FPGA嵌入式套件。所以现在我想构建一个比特流。所以我需要约束来说明哪个信号到哪个引脚。我下载了k7-embedded-trd-rdf0283.zip，并在itk7_emb_vdemo_top.xdc中找到。这看起来像我需要的。在Vivado 2015.2中，我添加了一个约束集，添加了源，添加了约束，并添加了上面的xdc文件。我在xdc文件中找到了一个合适的差分时钟对，复位和开关输入，然后修改了我的顶级设计以使用那些只有那些。接下来我尝试了实现。我得到了一大堆意想不到的严重警告，几乎所有警告都与xdc有关。我没想到这一点，也不知道该怎么办。（与* my 代码相关的唯一重要警告与FIFO和“get_property”错误有关。我认为这是因为还没有一个好的时钟输入。这应该在其他东西得到解决时解决。所以我的重点在这里是关于与参考设计xdc相关的严重警告。）（（（我不确定插件图像是如何在这个论坛上工作的。我正在插入错误和严重警告的屏幕抓取。如果你没有看到嵌入的图像，请将其作为附件查找。这表明我得到的错误，并暗示我有关如何通过他们的问题。）））（（（我不认为我可以附上k7_emb_vdemo_top.xdc，但是，因为我必须签署一份在线协议才能获得它。我不想通过在此发布它而意外违反该协议。如果需要是的，您可以通过访问https://www.xilinx.com/products/ ... .html#documentation获取一份副本，选中“Targeted Reference Designs”来缩短列表，然后下载UG985设计文件（部分底部）：http：//www.xilinx.com/member/forms/download/design-license.html？cid = 344718＆amp; filename = k7-embedded-trd-rdf0283.zip）））编辑：关于实际错误，请参阅第二张图片。到目前为止，我已经连接了所有端口。谢谢，赫尔穆特以上来自于谷歌翻译以下为原文 I did a bunch of simulation work, and that builds OK. It has warnings, but no errors. My target hardware is the Kintex-7 FPGA Embedded Kit. So now I want to build a bitstream. So I need constraints to say which signal goes to which pin. I downloaded k7-embedded-trd-rdf0283.zip and found within it k7_emb_vdemo_top.xdc. This looked like what I needed. In Vivado 2015.2, I added a constraint set, added sources, added constraints, and added the above xdc file. I found a suitable differential clock pair, reset, and switch input in the xdc file, then modified my top level design to use those and only those. Next I tried implementation. I got a whole slew of unexpected critical warnings, almost all of them associated with the xdc. I didn't expect this and don't know what to do about it. (The only critical warning relating to my* code relates to a FIFO and a "get_property" error. I believe this is due to not yet having a good clock input. That should resolve when the other stuff is resolved. So my focus here is on the critical warnings associated with the reference design xdc.) (((I'm not sure how insert image is working on this forum. I am inserting a screen grab of the errors and critical warnings. If you don't see the image embedded, please look for it as an attachment. This shows the errors I am getting and implies my questions about how to get past them.))) (((I don't think I can attach the k7_emb_vdemo_top.xdc, however, because I had to sign an online agreement to get it in the first place. I don't want to accidentally violate that agreement by posting it here. If need be, you can get a copy yourself by visiting https://www.xilinx.com/products/ ... .html#documentation , checking "Targeted Reference Designs" to shorten the list, and then downloading UG985 design files (bottom of section) at https://www.xilinx.com/member/fo ... ded-trd-rdf0283.zip ))) EDIT: regarding the actual error, see second image. I've connected all the ports so far as I can figure. Thanks, Helmut 0
2018-11-6 11:45:06　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答举报王林相关推荐 • kintex-7系列板和zynq-7评估板如何进行通信 1873 • 设备锁定到单个kintex板或kintex评估板组？ 1776 • 开发FPGA Kintex-7板子的PCIe与DDR模块高速通信，应该准备些什么？ 3359 • 为什么vivado 2013.2无法为zynq 7020主板创建嵌入式源代码？ 3014 • Kintex-7是否具有相同封装引脚兼容的不同器件？ 1601 • 请问Kintex-7评估板中包含西门子DMA逻辑评估核心吗？ 1613 • 如何在Kintex-7设计上测量VCCINT的静态电流？ 1504 • Kintex-7 FPGA KC705评估套件与PC接口如何读取数据？ 2112 • Kintex-7未使用的高性能引脚怎么办 2204 • 如何使用Kintex-7评估板KC705来实现DP1.2接收器？ 1962 2个回答

答案对人有帮助，有参考价值 0 None 以上来自于谷歌翻译以下为原文 Perhaps "nevermind". The first error was indeed the show stopper. Turns out the optimizer WAS removing all the leaf cells of my design. I had only connected INPUT pins to my top level. So I guess, with no outputs, it all got optimized away. DOH! So I added a single output. I realize this won't test my whole project, but one step at a time. While the slew of critical warnings remain, and I'll have to figure out if I care about them later, that original error did go away. Of course it was replaced by a different error relating to a clock connection error. I think I can deal with this. View solution in original post

2018-11-6 12:03:45 评论举报邝计嘉

答案对人有帮助，有参考价值 0 也许“没关系”。第一个错误确实是节目塞。结果是优化器WAS删除了我设计的所有叶子单元格。我只将INPUT引脚连接到顶层。所以我猜，没有输出，它都被优化了。 DOH！所以我添加了一个输出。我意识到这不会测试我的整个项目，而是一次一步。虽然一大堆关键警告仍然存在，而且我将不得不弄清楚我以后是否关心它们，原始错误确实消失了。当然，它被与时钟连接错误相关的不同错误所取代。我想我可以解决这个问题。以上来自于谷歌翻译以下为原文 Perhaps "nevermind". The first error was indeed the show stopper. Turns out the optimizer WAS removing all the leaf cells of my design. I had only connected INPUT pins to my top level. So I guess, with no outputs, it all got optimized away. DOH! So I added a single output. I realize this won't test my whole project, but one step at a time. While the slew of critical warnings remain, and I'll have to figure out if I care about them later, that original error did go away. Of course it was replaced by a different error relating to a clock connection error. I think I can deal with this.

2018-11-6 12:18:39 评论举报邝计嘉