完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
在我的.xdc文件中,我写了“set_property VREF {Y18 AE16 AD3 W4} [current_design]”来设置我的DDR3 DIMM接口的VREF引脚。
但在实施之后,Vivado发出一个严厉警告说 [Netlist 29-69]无法设置属性“VREF”,因为“design”类型的对象不存在该属性。 [ “E:/YCYK/FPGA/K7_325_DDR3_X14/TEST/TEST.srcs/constrs_1/imports/new/top.xdc”:449] 为什么消息意味着什么? 以上来自于谷歌翻译 以下为原文 In my .xdc file, I write "set_property VREF {Y18 AE16 AD3 W4} [current_design]" to set the VREF pins for my DDR3 DIMM interface. But after the implementation, Vivado give a critical warning that said [Netlist 29-69] Cannot set property 'VREF', because the property does not exist for objects of type 'design'. ["E:/YCYK/FPGA/K7_325_DDR3_X14/TEST/TEST.srcs/constrs_1/imports/new/top.xdc":449] Why does the message mean? |
|
相关推荐
15个回答
|
|
经过一些检查后,我确认VREF是一个仅支持某些CPLD系列且从未应用于FPGA的属性。
包含在Vivado的一些文档中,UG903和UG911是一个错误,引用将被删除。 从XDC中删除约束。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 After a bit of checking I confirmed that VREF was an attribute that was only supported for some CPLD families and never applied to FPGAs. The inclusion in some of the Vivado documentation, UG903 and UG911, is a mistake and the references will be removed. Remove the constraint from XDC. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
|
|
|
嗨,
您是否还试图在不启用GUI中的内部vref选项的情况下为特定DDR3引脚设置内部vref? 如果您将MIG用于DDR3 DIMM,我认为IP将根据您的GUI设置生成适当的约束。 你有没有检查过它,并且出于任何原因想要编辑xdc,你能分享更多的输入,比如哪个设备,工具版本等? -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi, Also are you trying to set internal vref for specific DDR3 pins without enabling internal vref option in the GUI? If you are using MIG for your DDR3 DIMM I think IP will generate appropriate constraints based on your GUI settings. Have you checked with it and wanted to edit xdc for any reason, can you share more inputs like which device, tool version etc? --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
|
|
|
仅当DDR3工作在800Mb / s以下时,才能使用内部vref。
所以我使用外部VREF。我使用的设备是Kintex7 325,-2速度 以上来自于谷歌翻译 以下为原文 The internal vref can be used only when the DDR3 working below 800Mb/s. So I used external VREF. The device I used is Kintex7 325, -2 speed |
|
|
|
ug911给出了将CONFIG VREF迁移到vivado的示例。
例子是: set_property VREF {E11 F11} [current_design] 以上来自于谷歌翻译 以下为原文 The ug911 gives an example of migrating CONFIG VREF to vivado. The example is: set_property VREF {E11 F11} [current_design] |
|
|
|
我尝试了这个,但vivado给出了上面的警告
以上来自于谷歌翻译 以下为原文 I tried this, but the vivado give the warning above |
|
|
|
|
|
|
|
对不起,这个话题有点困惑。
当我试图为DDR3存储体设置VREF引脚而不是设置VREF电压时,我遇到了那个严重的警告。 以上来自于谷歌翻译 以下为原文 I am sorry the topic is a little confused. I met that critical warning when I tried to set the VREF pin for DDR3 banks, not to set the VREF voltage. |
|
|
|
得到它,但我不确定你是否真的想要为基于MIG的设计指定约束xdc,因为特定字节组(仅输入-DQ)的vref引脚是固定的,并且MIG的名称类似于T0,1,2_vref。
... 你的设备包和DDR3 DQ接口的宽度是什么,放在哪些银行? 您是否经历过UG475的引脚列表.txt和验证的Y18 AE16 AD3 W4所有封装的vref引脚? 是MIG示例设计还是定制设计? 编辑: - 我还记得在您的IO.rpt文件中,您将看到在放置MIG的库中需要vref引脚的文本vref。 请使用MIG为您的设置实现默认引脚分配的设计,并检查工具是否正在检测DIMM的vref引脚 希望这可以帮助 问候, Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Got it, but I am not sure if you really want to specify that constraint in xdc for MIG based designs as the vref pins for specific byte groups(Inputs only- DQ) are fixed and are known to MIG named something like T0, 1, 2_vref.... What is your device package and DDR3 DQ interface width and placed in which banks? Have you gone through the pinout list .txt from UG475 and verified Y18 AE16 AD3 W4 are all vref pins for your selected package ? Is it MIG example design or custom design? Edit:- I also remember in on of your IO.rpt files you will see the text vref rquired for vref pins in the banks where MIG is placed. Please implemnet the design with default pinout given by MIG for your settings and check if the tool is detecting the vref pins for your DIMM Hope this helps Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
|
|
|
事情变得有线。
我尝试了可用于DDR3 SODIMM的示例设计,并在.xdc文件中添加了VREF pinsconstrains。 Vivado给出了同样的严重警告。 数据宽度为64。 我使用的设备是xc7k325tffg676-2,我检查了引脚文件。 Y18 AE16 AD3和W4是Bank 32和34的VREF引脚。我在两个bank中分配了所有DQ,DQS和DM引脚。 所有控制和地址引脚都在Bank 33中分配。 我的引脚分配基于示例设计,只是交换了一些引脚。 交换符合规则。 如果我在.xdc文件中添加VREF pinsconstrains,示例设计和自定义设计都会给出相同的严重警告。 示例设计中的.xdc文件不会限制VREF引脚。 我认为用户应该将VREF引脚添加到他们的设计中,以便让Vivado验证分配。 这是正确而安全的方式。 但Vivado并不认为它对对象“设计”有效。 这可能是Vivado 2013.2的一个错误。 我没有Vivado的新版本。 有人可能会在新版本中试用它。 以上来自于谷歌翻译 以下为原文 Things become wired. I tried the example design which can be used for DDR3 SODIMM, and add the VREF pins constrains in the .xdc file. The Vivado gives the same critical warning. Data width is 64. The device I used is xc7k325tffg676-2, and I checked the pinout file. Y18 AE16 AD3 and W4 are the VREF pins for Bank 32 and 34. I allocated all DQ, DQS and DM pins in the two banks. All the control and address pins allocated in Bank 33. My pin assignment was based on the example design, and just exchanged some pins. The exchangement complied with the rules. Both the example design and the custom design give the same critical warning if I add the VREF pins constrains in the .xdc file. The .xdc file from the example design doesn't constrain the VREF pins. I think users should add the VREF pins into their design in order to make the Vivado verify the assignments. That is the correct and safe way. But the Vivado doesn't consider it as valid for object "design". This maybe a bug of Vivado 2013.2. I do not have a new version of Vivado. Someone may try it in a new version. |
|
|
|
嗨,
我得到了你的意思,但从MIG的角度来看,你不需要那个约束。 如果您担心其余的设计可能会占用这些引脚,您可以尝试使用禁止constarint 但我认为当vref引脚与MIG预期相同时,Vivado不应该有任何理由给出严重警告。 我将尝试在我的最后复制它并将提交CR。 谢谢让我们注意到这个 问候, Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi, I got what you are saying but from MIG perspective you do not need that constraint. If you worry the rest of your design might occupy those pins you can try to use prohibit constarint But I think there should not be any reason why Vivado gives critical warning when the vref pins are same as MIG expected. I will try replicate it at my end and will file CR. Thanks for bringing this to our attention Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
|
|
|
嗨,
vsrunga,非常感谢。 我将在下次详细描述我的问题。 如果对此问题有任何结论,请回复我,谢谢! 以上来自于谷歌翻译 以下为原文 Hi, vsrunga, thanks a lot. I will describe my question as detailed as possible next time. If there is any conclusion about this problem, please reply me, thank you! |
|
|
|
设备的VREF引脚分配由软件自动处理。
您在哪里读到需要在设计中添加“set_property VREF {Y18 AE16 AD3 W4} [current_design]”约束? ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 The allocation of VREF pins of the device are handled automatically by the software. Where did you read that you need to add the "set_property VREF {Y18 AE16 AD3 W4} [current_design]"constraint to your design? ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
|
|
|
经过一些检查后,我确认VREF是一个仅支持某些CPLD系列且从未应用于FPGA的属性。
包含在Vivado的一些文档中,UG903和UG911是一个错误,引用将被删除。 从XDC中删除约束。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 After a bit of checking I confirmed that VREF was an attribute that was only supported for some CPLD families and never applied to FPGAs. The inclusion in some of the Vivado documentation, UG903 and UG911, is a mistake and the references will be removed. Remove the constraint from XDC. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
|
|
|
|
|
|
|
|
|
|
|
只有小组成员才能发言,加入小组>>
2317 浏览 7 评论
2727 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2213 浏览 9 评论
3292 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2361 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
649浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
456浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
216浏览 1评论
664浏览 0评论
1857浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-9-27 06:18 , Processed in 1.458662 second(s), Total 104, Slave 88 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号