哪个MMCM与v7中的BUFGGTRL_X0Y8处于同一半？

嗨，
这是一个小脚本我使用om实现设计来导出BUFG位置。
set bufg_elements [get_cells -hierarchical -filter {PRIMITIVE_TYPE ==“CLK.gclk.BUFG”||
PRIMITIVE_TYPE ==“CLK.gclk.BUFGCTRL”}]; foreach bufg $ bufg_elements {set LOC_property [get_property LOC [get_cells $ bufg]]; put“BUFG instance ”$ bufg “置于site ”$ LOC_property “
“;
}
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）
在原帖中查看解决方案



以下为原文

Hi,
 
Here is a small script I use om implemented design to export the BUFG locations.
 
set bufg_elements [get_cells -hierarchical -filter { PRIMITIVE_TYPE == "CLK.gclk.BUFG" || PRIMITIVE_TYPE == "CLK.gclk.BUFGCTRL" } ];
foreach bufg $bufg_elements {
set LOC_property [get_property LOC [get_cells $bufg]];
puts "BUFG instance "$bufg" is placed at site "$LOC_property"";
}
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post

嗨，
他们确实在同一半。
你看到一些问题吗？
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
They are indeed in the same half.
 
Do you see some issue?
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

嗨，
很高兴看到你还在线。
:)
它报告如下：
34431时钟规则：rule_mmcm_bufg34432状态：FAIL34433规则说明：驱动BUFG的MMCM必须放置在设备343434的同一半侧（顶部/底部）u_fpga_dut_clk / u_v7_disp_hub_clk / mmcm_adv_inst（MMCME2_ADV.CLKOUT0）锁定到MMCME2_ADV_X1Y1（在SLR 0中）
）34435 u_fpga_dut_clk / u_v7_disp_hub_clk / clkout1_buf（BUFG.I）被锁定为BUFGCTRL_X0Y8（在SLR 0中）34436错误：以上也是非法时钟规则34437解决方法：



以下为原文

Hi,
Glad to see you are still online . :)
 
It report like this:
34431 Clock Rule: rule_mmcm_bufg
34432 Status: FAIL
34433 Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
34434 u_fpga_dut_clk/u_v7_disp_hub_clk/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is locked to MMCME2_ADV_X1Y1 (in SLR 0)
34435 u_fpga_dut_clk/u_v7_disp_hub_clk/clkout1_buf (BUFG.I) is locked to BUFGCTRL_X0Y8 (in SLR 0)
34436 ERROR: The above is also an illegal clock rule
34437 Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_fpga_dut_clk/u_v7_disp_hub_clk/clkout0] >
 

嗨，
我尝试了一个具有BUFG和MMCM相同位置的示例设计，我没有看到任何错误。
我想你的设计还有其他原因导致失败。
你能在这里附上实施日志文件吗？
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi, 
 
I tried with an example design with same locations of BUFG and MMCM, I dont see any error.
 
I guess there is some other reason for failure in your design.
 
Can you attach implementation log file here.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

嗨，
谢谢你的试用。
我认为这可能是由于最高错误造成的：
34409阶段2.1.5.2 IO＆amp;
Clk Clean Up34410错误：[放置30-169]具有时钟功能的IO引脚和BUFH对的次优放置。
如果此子设计可接受此子优化条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUT E约束将此消息降级为WARNING。
但是，强烈建议不要使用此覆盖。
这些示例可以直接在.xdc文件中使用以获得此时钟规则.34411 3441234413 u_fpga_dut_clk / ibufg_gclk1（IBUFDS.O）被锁定到IOB_X0Y326（在SLR 2中）34414 u_fpga_dut_clk / u_v7_disp_hub_clk / clkin1_buf（BUFH.I）被锁定
到BUFHCE_X1Y12（在SLR 0中）3441534416上述错误可能与其他连接的实例有关。
以下是34417所有相关时钟规则及其各自实例的列表.3441834419时钟规则：rule_bufh_bufr_ramb34420状态：PASS34421规则说明：同一时钟区域中的寄存器缓冲区必须驱动的总数少于344222，而不是区域容量34423 u_fpga_dut_clk / u_v7_disp_hub_clk
/ clkin1_buf（BUFH.O）被锁定为BUFHCE_X1Y12（在SLR 0中）3442434425时钟规则：rule_bufhce_mmcm34426状态：PASS34427规则描述：驱动MMCM的BUFH必须都在同一个时钟区域34428 u_fpga_dut_clk / u_v7_disp_hub_clk / clkin1_buf（BUFH.O）
被锁定为BUFHCE_X1Y12（在SLR 0中）34429 u_fpga_dut_clk / u_v7_disp_hub_clk / mmcm_adv_inst（MMCME2_ADV.CLKIN1）被锁定到MMCME2_ADV_X1Y1（在SLR 0中）3443034431时钟规则：rule_mmcm_bufg34432状态：FAIL34433规则说明：驱动BUFG的MMCM必须放在
设备343434的相同半侧（顶部/底部）u_fpga_dut_clk / u_v7_disp_hub_clk / mmcm_adv_inst（MMCME2_ADV.CLKOUT0）被锁定到MMCME2_ADV_X1Y1（
在SLR中0）34435 u_fpga_dut_clk / u_v7_disp_hub_clk / clkout1_buf（BUFG.I）被锁定到BUFGCTRL_X0Y8（在SLR 0中）34436错误：以上也是非法时钟规则34437解决方法：3443834439时钟规则：rule_mmcm_bufg34440状态：FAIL34441规则描述：MMCM
驱动BUFG必须放在设备的同一半侧（顶部/底部）34442 u_fpga_dut_clk / u_v7_disp_hub_clk / mmcm_adv_inst（MMCME2_ADV.CLKOUT1）被锁定到MMCME2_ADV_X1Y1（在SLR 0中）34443 u_fpga_dut_clk / u_v7_disp_hub_clk / clkout2_buf（BUFG.I）是
锁定到BUFGCTRL_X0Y9（在SLR 0中）34444错误：以上也是非法时钟规则34445解决方法：



以下为原文

Hi,
Thanks for you trial.
I think it may result from the top error :
 
34409 Phase 2.1.5.2 IO & Clk Clean Up
34410 ERROR: [Place 30-169] Sub-optimal placement for a clock-capable IO pin and BUFH pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUT E constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to ove rride this clock rule.
34411 < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_fpga_dut_clk/gclk1_in] >
34412
34413 u_fpga_dut_clk/ibufg_gclk1 (IBUFDS.O) is locked to IOB_X0Y326 (in SLR 2)
34414 u_fpga_dut_clk/u_v7_disp_hub_clk/clkin1_buf (BUFH.I) is locked to BUFHCE_X1Y12 (in SLR 0)
34415
34416 The above error could possibly be related to other connected instances. Following is a list of
34417 all the related clock rules and their respective instances.
34418
34419 Clock Rule: rule_bufh_bufr_ramb
34420 Status: PASS
34421 Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
34422 than the capacity of the region
34423 u_fpga_dut_clk/u_v7_disp_hub_clk/clkin1_buf (BUFH.O) is locked to BUFHCE_X1Y12 (in SLR 0)
34424
34425 Clock Rule: rule_bufhce_mmcm
34426 Status: PASS
34427 Rule Description: A BUFH driving an MMCM must both be in the same clock region
34428 u_fpga_dut_clk/u_v7_disp_hub_clk/clkin1_buf (BUFH.O) is locked to BUFHCE_X1Y12 (in SLR 0)
34429 u_fpga_dut_clk/u_v7_disp_hub_clk/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X1Y1 (in SLR 0)
34430
34431 Clock Rule: rule_mmcm_bufg
34432 Status: FAIL
34433 Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
34434 u_fpga_dut_clk/u_v7_disp_hub_clk/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is locked to MMCME2_ADV_X1Y1 (in SLR 0)
34435 u_fpga_dut_clk/u_v7_disp_hub_clk/clkout1_buf (BUFG.I) is locked to BUFGCTRL_X0Y8 (in SLR 0)
34436 ERROR: The above is also an illegal clock rule
34437 Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_fpga_dut_clk/u_v7_disp_hub_clk/clkout0] >
34438
34439 Clock Rule: rule_mmcm_bufg
34440 Status: FAIL
34441 Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
34442 u_fpga_dut_clk/u_v7_disp_hub_clk/mmcm_adv_inst (MMCME2_ADV.CLKOUT1) is locked to MMCME2_ADV_X1Y1 (in SLR 0)
34443 u_fpga_dut_clk/u_v7_disp_hub_clk/clkout2_buf (BUFG.I) is locked to BUFGCTRL_X0Y9 (in SLR 0)
34444 ERROR: The above is also an illegal clock rule
34445 Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_fpga_dut_clk/u_v7_disp_hub_clk/clkout1] >

嗨，
MRCC / SRCC可以驱动BUFH，它位于相同或水平相邻的时钟区域。
在你的情况下，IO和BUFH完全不同的SLR，因此错误。
以下是UG472的快照
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
The MRCC/SRCC can drive BUFH which is in same or horizontally adjacent clock region.
 
In your case the IO and BUFH are in different SLR's totally and hence the error.
 
Below is snapshot from UG472
 

 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

谢谢。
现在我再次自己放置所有bufg并重新运行设计。
但我仍然有7个未布线的网。但这次MMCM和BUFG在同一个SLR中。我不知道为什么。
34898阶段9验证路由网络34899严重警告：[路由35-54]网络：u_fpga_dut_clk / v7_pll_dyn_rg_u3 / clk_out1_v7_pll_dyn_rg未完全路由.349分辨率：运行report_route_status以获取更多信息.34901严重警告：[路线35-54]网络：u_fpga_dut_clk /
v7_mmcm_dyn_sor_rg_hdmi_u2 / clkout0未完全路由.34902解决方案：运行report_route_status以获取更多信息.34903严重警告：[路线35-54] Net：u_fpga_dut_clk / v7_pll_dyn_rg_u3 / rg3_clk_nobuf未完全路由.34904解决方案：运行report_route_status以获取更多信息.34905 CRITICAL
警告：[Route 35-54] Net：u_fpga_dut_clk / v7_mmcm_dyn_sor_rg_hdmi_u2 / rg2_clk_nobuf未完全路由.34906解决方案：运行report_route_status以获取更多信息.34907严重警告：[Route 35-54] Net：u_fpga_dut_clk / v7_pll_dyn_rg_u3 / sor3_clk_nobuf未完全路由
.34908解决方法：运行report_route_status以获取更多信息.34909严重警告：[Route 35-54] Net：u_fpga_dut_cl
k / v7_mmcm_dyn_sor_rg_hdmi_u2 / sor2_clk_nobuf未完全路由.34910解决方法：运行report_route_status以获取更多信息.34911严重警告：[路由35-54] Net：u_fpga_display / u_DP_sor0 / u_gtx_clk / inst / dp_162m_source未完全路由.34912解决方案：运行report_route_status
更多信息.35913关键警告：[路线35-7]设计有5个不可路由的引脚，可能由放置问题引起.34914严重警告：[路线35-8]设计有14个未布线的引脚，仍可到达。



以下为原文

Thanks.
Now I placed all bufg by myself again and re-run the design.
But I still got 7 unrouted nets.But this time the MMCM and the BUFG are in the same SLR.I don't know why.
 
34898 Phase 9 Verifying routed nets
34899 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_pll_dyn_rg_u3/clk_out1_v7_pll_dyn_rg is not completely routed.
34900 Resolution: Run report_route_status for more information.
34901 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_mmcm_dyn_sor_rg_hdmi_u2/clkout0 is not completely routed.
34902 Resolution: Run report_route_status for more information.
34903 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_pll_dyn_rg_u3/rg3_clk_nobuf is not completely routed.
34904 Resolution: Run report_route_status for more information.
34905 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_mmcm_dyn_sor_rg_hdmi_u2/rg2_clk_nobuf is not completely routed.
34906 Resolution: Run report_route_status for more information.
34907 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_pll_dyn_rg_u3/sor3_clk_nobuf is not completely routed.
34908 Resolution: Run report_route_status for more information.
34909 CRITICAL WARNING: [Route 35-54] Net: u_fpga_dut_clk/v7_mmcm_dyn_sor_rg_hdmi_u2/sor2_clk_nobuf is not completely routed.
34910 Resolution: Run report_route_status for more information.
34911 CRITICAL WARNING: [Route 35-54] Net: u_fpga_display/u_DP_sor0/u_gtx_clk/inst/dp_162m_source is not completely routed.
34912 Resolution: Run report_route_status for more information.
34913 CRITICAL WARNING: [Route 35-7] Design has 5 unroutable pins, potentially caused by placement issues.
34914 CRITICAL WARNING: [Route 35-8] Design has 14 unrouted pins, that are still reachable.

嗨，vemulad
你能帮我看一下吗？
或者您需要新的dcp文件吗？



以下为原文

Hi,vemulad
Would you please to help me to have a look at it?
Or Do you need the new dcp file?
 

嗨，
我们需要检查错误中提到的网络的连接性以及相关逻辑的位置。
你能和我分享新的postcheckcheckpoint文件吗？
您可以使用相同的ezmove链接。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
We need to check the connectivity of the net mentioned in the error and also the placement of the associated logic.
 
Can you share me the new post route checkpoint file? You can use the same ezmove link.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

当然。我会寄给你检查站。
我不知道日志有什么问题。我只是得到了上面的信息。



以下为原文

Sure.I will send you the checkpoint. I cannot  tell what is wrong from the log.I just got the information as above.

好的，将等待您的检查点文件。
--Deepika。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Ok, will wait for your checkpoint file.
 
--Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

嗨，
我只是在前面的dcp中添加了一些约束。新的dcp太大而无法传输。
你能改变约束吗？



以下为原文

Hi,
I just add some constraint with the previous dcp.The new dcp is too large to transfer.
 
Could you change the constraint only?

嗨，
好的，你能告诉我新的限制吗？
我会尝试使用旧的DCP。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
Ok, Can you tell me the new constraints? I will try to run with old DCP.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

嗨，
我已通过ezmove邮件发送给您。



以下为原文

Hi,
I have send you through ezmove mail.

嗨，
vemlad
我更改了设计代码。
我想知道在运行place_ports之后，在哪里可以获得所有bufg放置位置的报告？



以下为原文

Hi,
vemlad
I have changed my design code.
I want to know where can I get the report of the location where all the bufg are placed after I run place_ports?
 

嗨，
这是一个小脚本我使用om实现设计来导出BUFG位置。
set bufg_elements [get_cells -hierarchical -filter {PRIMITIVE_TYPE ==“CLK.gclk.BUFG”||
PRIMITIVE_TYPE ==“CLK.gclk.BUFGCTRL”}]; foreach bufg $ bufg_elements {set LOC_property [get_property LOC [get_cells $ bufg]]; put“BUFG instance ”$ bufg “置于site ”$ LOC_property “
“;
}
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
Here is a small script I use om implemented design to export the BUFG locations.
 
set bufg_elements [get_cells -hierarchical -filter { PRIMITIVE_TYPE == "CLK.gclk.BUFG" || PRIMITIVE_TYPE == "CLK.gclk.BUFGCTRL" } ];
foreach bufg $bufg_elements {
set LOC_property [get_property LOC [get_cells $bufg]];
puts "BUFG instance "$bufg" is placed at site "$LOC_property"";
}
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

非常感谢。



以下为原文

Thanks very much.