“两个IDAC可以并行组成一个8位IDAC”是什么意思？

Yocchi
你的示意图是正确的。并行增加IDAC是增加最大电流和增加分辨率的一种方式。几年前，我为PSoC 3/5部分做了一个附加注释，但是概念是相同的。参见Copress AppNo.AN64 265。
当做，
作记号



     以下为原文
  Yocchi,
Your schematic is correct. Adding iDACs in parallel is one way of increasing maximum current and adding resolution.  I wrote an appnote on doing this several years ago for the PSoC 3/5 parts, but the concept is the same.  See Cypress Appnote AN64275.
 
Regards,
Mark

嗨，马克
谢谢你的回复。
在PSoC040S的情况下，我认为14位DAC可以放在下面两个7位DAC上。
对吗？
我们担心故障。
不幸的是，PSoC040S没有“频闪模式”。我们能用其他方法消除它吗？
两个DAC都不能在同一时间写入。这种故障可以通过设置“频闪模式”来消除。
参数到每个DAC的定制器中的“外部”。然后将两个选通脉冲输入连接到同一个时钟源。
最好的问候，
约奇



     以下为原文
  Hi, Mark
 
Thank you for your reply.
In case of PSoC4000S, I think 14bit DAC can be put with two 7bit DAC like below.
Is it right?



 
And we are anxious about glitch.
Unfortunately, PSoC4000S does not have "Strobe_Mode". Can we eliminate it using other method?
  both DACs cannot be written at the exact same time. This glitch can be eliminated by setting the „Strobe_Mode‟
  parameter to „External‟ in the customizer of each DAC. Then connect both strobe inputs to the same clock source.
 
Best regards,
Yocchi

将上面所示的两个IDAC组合起来，可以用于制作一个更大的14位IDAC。



     以下为原文
  Combining the two IDACs as you show above should work for making a larger 14-bit IDAC.

Yocchi
只有这么远，你可以去，你真的不能得到14位的两个7位DAC。在纸上你可能能够，但是硬件的绝对DNL没有改变，更坏的情况是7个比特的1个LSB，8个比特的2个LSB，9个比特的4个LSB等等。你可以得到一个可用的9位，但是DNL可能超过你能容忍的。
Stobe模式，我一直要求它，但因为这些DAC主要用于帽子感，所以觉得不需要它。如果我有我的方式，我们所有的DAC都会有一个双缓冲闪存模式。我喜欢PSoC 3/5中的VIDACs，因为它们的灵活性，选通/直接模式，电压/电流，以及DAC总线！
作记号



     以下为原文
  Yocchi,
There is only so far you can go and you really can't get 14-bits out of two 7-bit DACs.  On paper you might be able to, but the absolute DNL of the hardware does not change, worse case it is 1 LSB for 7 bits, 2 LSBs for 8 bits, 4 LSBs for 9 bits, etc. You may be able to get a usable 9-bits, but the DNL may be more than you can tolerate.
 
Stobe mode, I keep asking for it, but since these DACs were primarily used for Cap Sense, it was felt there wasn't a need for it.  If I had my way, ALL of our DACs would have a double-buffered strobe mode.  I love the viDACs in PSoC 3/5 because of their flexibility, strobe/direct mode, voltage/current, and the DAC Bus!
 
Mark

作记号，
我还让IDAC的双缓冲。目前PSOC5 IDAC8是单缓冲的，因此无法使用硬件总线填充多个IDAC的缓冲器，然后同时启用输出。
ODISSEY1



     以下为原文
  Mark,
I also second to make IDAC's double-buffered. Currently PSoC5 IDAC8 is single buffered, so there is no way to use hardware bus to populate buffers of several IDACs and then enable the outputs simultaneously.
/odissey1

这是与PSoC 3 / 5 DAC总线正确，闸门荷载数据直接从总线输出。当使用CPU或DMA写的数据，PSoC 3/5 vidacs双缓冲。直到选通信号脉冲，输出才被更新。
作记号



     以下为原文
  That is correct with the PSoC 3/5 Dac Bus, the strobe loads the data directly from the bus to the output.  When using the CPU or DMA to write the data, the PSoC 3/5 viDACs are double buffered.  The output isn't updated until the strobe signal is pulsed.
 
Mark