斯巴达6为什么两个相同的“when else”语句可能导致不同的实现

你得到了什么信息？
你应该在这里复制并粘贴它们。
XST报告合成后的状态是什么？
我认为eop_wr信号已被优化，但输入/输出端口保持不变，因为它们存在于实体级别。
无法确切地看到所有逻辑如何相互作用（例如pkt_wr_EOP和pkt_we来自何处？这些信号如何变化？），很难说明实现的不同之处。
模拟pre / post_synthesis时你能看到什么？
问候，
霍华德
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Exactly what messages do you get? You should copy and paste them here.
 
What does the XST report state after synthesis?
 
It looks to me like that the eop_wr signal has been optimised away but the input/output ports maintain because they exist at an entity level.
 
Without being able to see exactly how all of your logic interacts (e.g. where do pkt_wr_EOP and pkt_we come from? How do those signals change?), it is difficult to state why the implementation is different.
 
What can you see when you simulate pre/post_synthesis?
 
Regards,
 
Howard
  
----------
"That which we must learn to do, we learn by doing." - Aristotle

霍华德
谢谢你的回复。
我发现了问题。
这是因为该信号不会驱动上层组件中的任何信号。
但是为什么编译器没有给我一个警告，就像信号没有负载一样。
我还有一个小问题，当我尝试实现我的一个组件时，我得到两个警告：
警告：NgdBuild：452  - 逻辑网'p01_vc / vc_req_id'没有driverWARNING：NgdBuild：452  - 逻辑网'p01_vc / vc_req_id'没有驱动程序
实际上有两个信号被创建为在子组件中使用的虚拟通道id。
它们不连接任何驱动程序。 
gen_vcids：process（rst，clk）begin lgen：for I in NOCEM_NUM_VC-1 downto 0 loop vc_myid_conv（I）end loop;
结束过程;
这些警告会影响我的最终PAR设计吗？
或者他们将转换为功能性LUT。



以下为原文

Howard
 
Thanks for you response. I find the problem. It's due to that this signal doesn't drive any signals in the very upper level component. But why the compiler didn't give me a warning like the signal doesn't have a load.
 
I still have a small problem that when I try to implememt one of my component, I get two warnings like:
 
WARNING:NgdBuild:452 - logical net 'p01_vc/vc_req_id<1><0>' has no driver
WARNING:NgdBuild:452 - logical net 'p01_vc/vc_req_id<0><1>' has no driver
 
There two signals actully are created as virtual channel id that used in sub-component. They don't connect to any drivers.
 
    gen_vcids : process(rst,clk)
    begin
        lgen : for I in NOCEM_NUM_VC-1 downto 0 loop
              vc_myid_conv(I) <= CONV_STD_LOGIC_VECTOR(2**I, NOCEM_VC_ID_WIDTH);
        end loop;
    end process;
 
Will these warning affect my final PAR design? Or they'll be translate to functional LUT.

首先，我不知道vc_req_id和vc_myid_conv是如何相关的。
我不可能说出为什么这些工具发出了警告，而不是说这些工具在这些问题上并不常见。
Ngdbuild：452是警告设计者可能未连接的信号。
如果这很重要，那么你应该采取措施避免它。
PAR无法路由无人信号。
无人驾驶信号是没有输入其值的信号。
您应该考虑循环如何驱动该信号的值。
问候，
霍华德
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Firstly, I cannot tell how vc_req_id and vc_myid_conv are related. It is impossible for me to say why the tools have issued a warning other than to say that the tools are not often wrong in these matters.
 
Ngdbuild:452 is a warning to alert the designer to a possibly unconnected signal. If this is important, then you should take steps to avoid it. A driverless signal will likely not be routed by PAR. A driverless signal is one that has no input to its value. You should consider how your loop is DRIVING the value of that signal.
 
Regards,
 
Howard
 
----------
"That which we must learn to do, we learn by doing." - Aristotle