帮助Coregen：MMCM参数选项

是，
如果在多个地区需要它，那么它就是全球性的。
由于您已经在设计中使用了时钟，并且如果它已经在BUFG上，输出信号名称现在可以连接到其他东西。
Austin Lesea主要工程师Xilinx San Jose
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以下为原文

Yes,

If it is needed in more than one region, that makes it global.  Since you already have the clock in your design, and if it is already on a BUFG, the output signal name may now be connected to something else.
 
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

好，
你想要什么？
60 MHz时钟输入来自某处，并且有一些抖动。
如果你不知道的话，我会输入50 ps，因为晶体振荡器源的频率从25ps到可能高达100ps，具体取决于它们的质量。
至于输出是什么驱动的：它是在全球范围内，在本地使用吗？
BUFG是全局缓冲区。
请查看MMCM用户指南，了解详细信息。
http://www.xilinx.com/support/documentation/user_guides/ug362.pdf
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Well,
 
What do you want?

A 60 MHz clock input comes from somewhere, and has some jitter.
 
I would put in 50 ps, if you do not know, as cyrstal oscillator sources are from 25ps to perhaps as much as 100ps, depending on their quality.

As for what the output is driving:  is it to be used globally, locally?  A BUFG is the global buffer.  Look at thge MMCM user's guide for the details.
 
http://www.xilinx.com/support/documentation/user_guides/ug362.pdf
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢奥斯汀。
我在.PAR文件中找到了这个。
clkm是我的MMCM输入clk所以我应该将源设置为全局缓冲区，对吧？
**************************
生成时钟报告
**************************
+ --------------------- + -------------- + ------ + -----
-  + ------------ + ------------- +
|
时钟网|
资源|锁定|扇出|净偏差（ns）|最大延迟（ns）|
+ --------------------- + -------------- + ------ + -----
-  + ------------ + ------------- +
|
clkm | BUFGCTRL_X0Y31 |
没有|
4612 |
0.455 |
2.035 |
我阅读了这份文件，这是非常好的信息。
我很确定我有可用的BUFG，但时钟仅用于一个组件，尽管它占整个设计的40％左右。
虽然全球时钟和本地时钟之间有什么区别？
我相信不止一个地区需要时钟，那么它是否具有全球性？
谢谢



以下为原文

Thanks Austin. I found this in my .PAR file. clkm is my MMCM input clk so I should set the source as global buffer, right?
 
**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|                clkm |BUFGCTRL_X0Y31| No   | 4612 |  0.455     |  2.035      |I read the document and it was pretty good information. I'm pretty sure I have available BUFG's, but the clock is only used in one component, although it is about 40% of the whole design. What is the difference between global vs local clocks though? I believe the clock will be needed in more than one region, so does that make it global?
 
Thanks
 

是，
如果在多个地区需要它，那么它就是全球性的。
由于您已经在设计中使用了时钟，并且如果它已经在BUFG上，输出信号名称现在可以连接到其他东西。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Yes,

If it is needed in more than one region, that makes it global.  Since you already have the clock in your design, and if it is already on a BUFG, the output signal name may now be connected to something else.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

它被扇出（连接）到超过4,000个其他元素（负载）。
Austin Lesea首席工程师Xilinx San Jose



以下为原文

It is fanned out (connected) to over 4,000 other elments (loads).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

尝试在PlanAhead中进行合成时出错。
如果我的时钟缓冲区将用于可重新配置的分区，那么我必须选择BUFHCE，而不是BUFGCE？



以下为原文

I have gotten an error when trying to synthesize in PlanAhead. If my clock buffer is going to be used in a reconfigurable partition, then I must choose BUFHCE, not BUFGCE?

是。
可重配置性增加了许多限制。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Yes.
 
Reconfigurability adds a number of restrictions.



Austin Lesea
Principal Engineer
Xilinx San Jose

我需要提前注意的任何其他限制吗？
我希望有一个覆盖多个时钟域的动态分区。
我最好将缓冲区作为BUFGCE放在静态逻辑中还是在可重构逻辑中使用BUFHCE？



以下为原文

Any other restrictions that I need to be aware of ahead of time? I wish to have a dynamic partition covering multiple clock domains. Am I better off putting the buffer as a BUFGCE in the static logic or having a BUFHCE in the reconfigurable logic?

我建议将基本结构内容放在不可重新配置的部分中。
IO，时钟等都是最好的保持静态。
随心所欲地改变逻辑。
这是最简单和最容易做到的事情，并且会导致最少的头痛和问题。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

I recommend putting the basic structure stuff in the non-reconfigurable part.
 
IO, clocks, etc. are best all kept static.
 
Change the logic all you wish.
 
That is the simplest and easiest to do, and will lead tio the fewest headaches and problems.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose