模拟后的MAP出现一些问题

我正在做一个关于图像处理的项目。
我的同事完成了界面部分，经过船上验证后，效果很好。
我正在做algm部分，在我的工作之前，我想为接口部分构建测试平台以查看其内部信号。
但是，在构建测试平台之后，再次实现此前一个项目。
它有一些MAP问题。
如下：
位置：1333  - 具有输入/输出编程的IOB锁定到不支持此类值的Bank 1标准：名称= LVDS_25，VREF = NR，VCCO = 2.50，TERM = NONE，DIR = BIDIR，DRIVE_STR = NRList of
锁定的IOB：MCB1_DDR3_XDQS MCB1_DDR3_XDQS MCB1_DDR3_DQS MCB1_DDR3_DQS
移动测试台后，问题仍然存在。
我不知道。
似乎测试平台改变了一些东西。
ps：在这个项目中，使用了mig core。
芯片是斯巴达-6
谢谢大家。



以下为原文

I am doing a project about image processing. My colleague finished the interface part, and after verification on board, it works well. I am doing the algm part, before my work, I want to build the testbench for the interface part to see its internal signal. But, after I building the testbench, implement this former project again. It got some MAP problem. as follows:  

Place:1333 - Following IOB's that have input/output programming are locked to the bank 1 that does not support such values
IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = NR
List of locked IOB's:
MCB1_DDR3_XDQS<0>
MCB1_DDR3_XDQS<1>
MCB1_DDR3_DQS<0>
MCB1_DDR3_DQS<1>

after moving the testbench, the problem still exist. I have no idea about it. It seems the testbench changes something in uut.

ps: in this project, mig core is used. and the chip is spartan-6

Thank you everybody.