地图错误：不确定此问题的原因

siteSLICE_X79Y89不存在，因为该位置对应于切片结构中的孔。



以下为原文

The site SLICE_X79Y89 doesn't exist as that location corresponds to a hole in the slice fabric.

嗨Bwade，
感谢您的回复。
在给定该区域的某个维度的情况下，我得到了具有16个对象实例的系统以进行布局和布线。
当我沿着x维度增加区域时，保持Y维度不变，我得到这个错误：
错误：位置：120  - 没有足够的站点放置所有选定的组件。使用备用算法可以规避这些故障中的一些（尽管可能需要更长的运行时间）。
如果您想启用此算法，请将环境变量XIL_PAR_ENABLE_LEGALIZER设置为1并尝试
我不确定如何/为什么我得到这个错误。
我用区域X成功，我增加了区域X，但工具说没有足够的空间。
为什么这是怎么回事？
谢谢，



以下为原文

Hi Bwade,
 
Thanks for your reply. I got the system with 16 instance of the object to place and route, given a certain dimension for the area. When I increase the area along the x-dimension, leaving the Y dimension untouched, I get this error:

布局器无法安装设计中的所有组件。
通常还会有一个Place：543错误，它提供了所涉及组件的详细信息。
你有这样的错误吗？
如果是这样，请专注于这些组件的放置约束。
当您增加区域组范围时，您是否正在侵占另一个区域组范围？
如果是这样，你可能会拥挤其他范围。
根据设计中时钟组件的类型和数量，时钟位置可能需要对您的设计进行额外的布局规划。
如果是这种情况，最好在时钟区域边界上对齐区域组，以便时钟布局器的附加约束与约束条件兼容。



以下为原文

The placer is having trouble fitting all the components in the design. Usually there will also be a Place:543 error that provides details of the components involved. Are you getting such an error? If so, concentrate on the placement constraints on those components. 
 
When you increase the area group range are you encroaching on another area group range? If so, you may be crowding that other range.
 
Depending on type and number of clock components in your design, the clock place may have to do additional floorplanning to your design. If that's the case it's a good idea to align your area groups on clock region boundaries so that the clock placer's additional constraints are compatible with your constraints.

bwade，
我确实得到了错误，提到哪些组件不适合给定区域。
但是，这些组件的放置面积小于显示错误时提供的面积。
在我的所有测试中，我不会重叠系统中不同对象实例的区域。
据我所知，你建议在芯片上使用area_groups不是跨时钟区域。
如果只有一个MMCM / PLL用于整个系统，你能详细说明为什么这会有所帮助吗？
我可能会理解你的建议。
谢谢，



以下为原文

bwade,
 
I do get the errors mentioning which components do not fit in the given area. But, these components were placed given a smaller area than that provided when the error is shown. In all my tests, I do not overlap areas for different instances of an object in my system.
 
From what I understand, you recommend having the area_groups not cross clock regions on the chip. Can you elaborate on why this would help, if only one MMCM/PLL is used for the whole system? I may noy be fully understanding your recommendation.
 
Thanks,

你没有使用BUFGCTRL吗？
如果您直接从MMCM / PLL驱动时钟，这非常局限于合法放置（一个时钟区域），并可能解释您的放置错误。



以下为原文

Are you using no BUFGCTRLs then? If you are driving your clocks directly from the MMCM/PLL that is very restricticting to legal placement (one clock region) and may explain your placement errors.

我正在使用Xilinx的时钟发生器。
Xilinx的时钟发生器使用单个MMCM / PLL原语，以及用于时钟信号的时钟缓冲器（BUFG等）。
所以，我相信时钟基础设施很好。
我不明白的是你的原始建议。
你建议让area_groups不是芯片上的跨时钟区域。
你能解释一下原因吗？
谢谢，



以下为原文

I'm using a clock generator from Xilinx. The clock generator from Xilinx uses a single MMCM/PLL primitive, as well as clock buffers (BUFG, etc...) for the clock signal. So, I believe  the clocking infrastructure is fine.
 
What I don't understand is your orignal suggestion. You recommend having the area_groups not cross clock regions on the chip. Can you explain why?
 
Thanks,

时钟布局器布局以时钟区域为单位计划设计（如果需要）。
您需要考虑用户布局规划如何与时钟布局器的时钟区域分配进行交互。
如果区域组范围与时钟区域边界重叠，则由于时钟约束，它可能会丢失其一些区域。
您需要考虑区域组约束是否也只是将太多时钟限制为时钟区域。



以下为原文

The clock placer floorplans the design (if necessary) in clock region units. You need to consider how your user floorplan will interact with the clock placer's clock region allocation. If an area group range overlaps a clock region boundary it may lose some of its area due to the clocking constraints. You need to consider whether your area group constraints are also simply constraining too many clocks to a clock region.