实施过程中的两个警告

看起来你为错误的设备系列生成了核心。
----------------------------是的，我这样做是为了谋生。



以下为原文

Looks like you generated the core for the wrong device family.
----------------------------Yes, I do this for a living.

对于警告：NgdBuild：931：
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此警告可以忽略，因为模拟中的PLL_BASE功能对于Virtex 5和Spartan 6是相同的.SIM_DEVICE仅影响DRP行为。
对于警告：NgdBuild：443：
=======================
解决方案1：如果您的设计使用IP核并且所讨论的SFF与此类核心相关联，则这可能是正常的。
在某些情况下，IP内核会使某些引脚浮动，期望它们在MAP期间会被修整。
有关更多详细信息，请参阅答案记录21718。解决方案2：如果所讨论的SFF原语是您设计的一部分的一部分，那么上游综合工具可能会以下游逻辑的方式优化设计
从这个SFF已经削减了你的设计。
请查阅您的综合报告，以确定是否发生了这种情况。



以下为原文

For WARNING:NgdBuild:931:
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This warning can be ignored, as the PLL_BASE functionality in simulation is the same for Virtex 5 and Spartan 6. The SIM_DEVICE only effects the DRP behavior.
 
For WARNING:NgdBuild:443:
=======================
 
Solution 1:
If your design uses IP cores and the SFF in question is associated with such a core, this may be normal.  In some scenarios, IP cores leave certain pins floating with the expectation that they will be trimmed during MAP.  Please consult Answer Record 21718 for more details.

Solution 2:
If the SFF primitive in question is part of a portion of your design which is critical, it is possible that the upstream synthesis tool is optimizing the design in such a way that the downstream logic from this SFF has been trimmed out of your design.  Please consult your synthesis report to determine if this is what is happening.

谢谢大家。



以下为原文

Thanks everybody.

我最初做了，我认为这是问题，然而，当我重建核心指定正确的设备我得到相同的警告。
b



以下为原文

I did at first and I thought that was the problem, however, when I rebuilt cores specifying correct device I got same warnings.
 
b