帮助CLOCK GENERATOR，MPMC和时钟缓冲器

你好
我正在尝试布线spartan6设计。我有一个MPMC模块，它实现了一个运行速度为400 mhz的LPDDR内存。我使用时钟发生器内核将400Mhz和400Mhz 180相位馈送到MPMC。
发电机配置菜单我可以选择使用缓冲区。我现在不明白..
当我选择在clkout0和clkout1输出上有缓冲区时，映射器会抱怨并要求我用UCF中的CONSTRAIN来纠正它。
../clock_generator0/PLL_CLOCKOUT0_BUFG_INST.O“CLOCK DEDICATED ROUTE FALSE;
./clock_generator0/PLL_CLOCKOUT1_BUFG_INST.O“CLOCK DEDICATED ROUTE FALSE;
好吧，在我这样做后，MAPPER继续前进并且路线或多或少。
现在如果我在时钟发生器菜单上直接进行更改（NO BUFFER）..我删除了UCF中的先前约束
Mapper失败它告诉我像PLL_BUFF没有被放置的东西。我怎么能放置那些缓冲区。
我以为
那些是我可以在时钟发生器上选择的缓冲器!!
请帮忙..！



以下为原文

Hi
I'm in the process of trying to route a spartan6 design .I have a MPMC module that implements a LPDDR memory running at 400 mhz .I use a clock generator core to feed the 400Mhz and 400Mhz 180 phase to the MPMC .In the clock generator configuration menu i can choose to use a buffer or not .Well I dont understand NOW ..
When i choose to have buffers on clkout0 and clkout1 outputs the mapper complains and asks me to correct it  with a CONSTRAIN in the UCF ..
../clock_generator0/PLL_CLOCKOUT0_BUFG_INST.O" CLOCK DEDICATED ROUTE FALSE ;
./clock_generator0/PLL_CLOCKOUT1_BUFG_INST.O" CLOCK DEDICATED ROUTE FALSE ;

Well after i do that the MAPPER goes ahead and routes more or less .

Now if i make the changes drectly on the clock generator menu ( NO BUFFER) .. I remove the previous constrains in UCF

The Mapper fails it tells me sometthing like the PLL_BUFF are not placed .How  can i place those buffers . I thought that
those were the buffers i could select on the Clock GENERATOR !!

Some help please ..!