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我在时序改进向导中读到,手动复制源可以减少扇出。
任何人都可以解释复制源的含义吗? 还有一个选项来设置最大扇出,我在合成属性对话框中默认为100000,而我在某处读到默认最大扇出为100.我不明白100000是否意味着100? 如果我想要一个扇出为25的寄存器自动重新复制,那么我应该将最大扇出数减少到24或以下吗? 非常感谢你! 问候。 消息由koyel.xilinx于03-31-2009 03:32 PM编辑 以上来自于谷歌翻译 以下为原文 I read in the timing improvement wizard that manually replicating a source reduces fanout. Can anyone explain what is meant by replicating the source? Also there is an option to set the maximum fanout, which I see is 100000 by default in the synthesis properties dialog box whereas I read somewhere that maximum fanout is by default 100. I do not understand if 100000 means 100? If I want a register having a fanout of 25 to be replcated automatically then should I reduce the maximum fanout number to 24 or something below? Thank you very much! Regards. Message Edited by koyel.xilinx on 03-31-2009 03:32 PM |
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对于某些设备,最大扇出为默认值500.对于新设备(例如V5),此数字为100000。
您可以将max_fanout约束应用于要由工具自动复制的寄存器。 如果更改max fanout合成属性的值,则将全局应用此值并影响整个设计。 这不是你所期望的。 您可以在XST用户指南中找到max_fanout约束的语法。 您应取消选中“等效寄存器删除”属性以防止删除重复的寄存器。 您也可以在代码中手动复制寄存器。 只需实例化另一个寄存器,用相同的驱动程序输入它,并使用它的输出来驱动一部分负载。 维维安 以上来自于谷歌翻译 以下为原文 For some devices the max fanout is default 500. For new devices (e.g. V5) this number is 100000. You can apply the max_fanout constraint to the register that you want to duplicated by the tool automatically. If you change value of the max fanout synthesis property, this will be applied globally and affect the whole design. This is not what you expect. You can find the syntax of max_fanout constraint in XST User Guide. You should uncheck "Equivalent Register Removal" property to prevent the duplicated register from being removed. You can also manually duplicate the register in your code. Just instantiate another register, feed it with the same driver and use it's output to drive a part of the loads. Vivian |
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“对于某些设备,最大扇出默认为500.对于新设备(例如V5),此数字为100000。”
好的,谢谢你的这些信息。 “您可以将max_fanout约束应用于要由工具自动复制的寄存器。” 但是有一个限制,我无法随机选择任何数字进行扇出,因为这会导致不必要的复制,这将消耗空间,我已经限制了这一点。 此外,所选数字似乎取决于合成和实施工具中设置的其他参数。 “如果更改max fanout合成属性的值,将全局应用并影响整个设计。这不是您所期望的。您可以在XST用户指南中找到max_fanout约束的语法。” 这就是我的意思。 “你应该取消选中”等效寄存器删除“属性,以防止删除重复的寄存器。你也可以手动复制你的代码中的寄存器。只需实例化另一个寄存器,用相同的驱动程序提供它并使用它的输出驱动部分 负荷。“ 我已经取消选中该选项。 现在我很清楚寄存器复制的含义,也感谢这些信息。 然而,我尝试了这个选项,因为我随机尝试了很多东西,但似乎驱动程序本身有一个很大的扇出,所以如果我驱动一个或多个单位没有区别。 增加寄存器会减少寄存器的扇形和扇出,而不会减少驱动器的扇形和扇出。 如果我错了,请纠正我,因为我仍在寻找解决问题的合理方法。 再次感谢。 干杯 以上来自于谷歌翻译 以下为原文 "For some devices the max fanout is default 500. For new devices (e.g. V5) this number is 100000." okay thanks for this information. "You can apply the max_fanout constraint to the register that you want to duplicated by the tool automatically." But there is a limit, I cannot randomly choose any number for fanout since that can result in unnecessary replications, which will consume space, which I am already limited to. Also the chosen number seems to be dependent on other parameters set in the synthesis and implementation tools. " If you change value of the max fanout synthesis property, this will be applied globally and affect the whole design. This is not what you expect. You can find the syntax of max_fanout constraint in XST User Guide. " This is what I meant exactly. "You should uncheck "Equivalent Register Removal" property to prevent the duplicated register from being removed. You can also manually duplicate the register in your code. Just instantiate another register, feed it with the same driver and use it's output to drive a part of the loads. " I have unchecked that option already. The meaning of register duplication is clear to me now and thanks for this information as well. However, I tried that option since I was trying many things randomly but it seemed the driver itself had a large fanout so there is no difference if I drive one or more units . Increasing the registers reduces the fanins and fanouts of the registers and not of the driver. Please correct me if I am wrong as I am still in the process of finding reasonable ways of solving the problem. Thanks again. cheers |
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MAX FANOUT有两个概念。
“如果更改max fanout合成属性的值”--- max fanout here是合成属性对话框中的综合全局属性。 此属性会影响整个设计。 “您可以将max_fanout约束应用于要由工具自动复制的寄存器。” --- man_fanout这里是XST的局部约束。 它可以应用于某些寄存器,并且仅影响它所应用的寄存器。 所以你需要的是max_fanout约束。 有关约束语法,请转到XST用户指南。 如果具有大扇出的驱动程序导致设计中出现计时问题,则需要复制此驱动程序。 维维安 以上来自于谷歌翻译 以下为原文 There are two concepts of MAX FANOUT. "If you change value of the max fanout synthesis property" --- max fanout here is a global property of synthesis which you see in the synthesis properties dialog box. This property affects the whole design globally. "You can apply the max_fanout constraint to the register that you want to duplicated by the tool automatically." ---man_fanout here is a local constraint of XST. It can be applied to certain register(s) and only affects the register(s) which it is applied to. So what you need is max_fanout constraint. Go to XST User Guide for the constraint syntax. If the driver having a large fanout caused timing problems in your design, you need to duplicate this driver. Vivian |
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viviany写道:MAX FANOUT有两个概念。
“如果更改max fanout合成属性的值”--- max fanout here是合成属性对话框中的综合全局属性。 此属性会影响整个设计。 “您可以将max_fanout约束应用于要由工具自动复制的寄存器。” --- man_fanout这里是XST的局部约束。 它可以应用于某些寄存器,并且仅影响它所应用的寄存器。 所以你需要的是max_fanout约束。 有关约束语法,请转到XST用户指南。 如果具有大扇出的驱动程序导致设计中出现计时问题,则需要复制此驱动程序。 维维安 这些信息非常有用。 我还在XST用户指南中读到,可以在XCF文件中设置其语法为的约束 BEGIN MODEL“entity_name”NET“signal_name”register_duplication = {yes | no | true | false}; END; 但如果我用它 BEGIN MODEL“entity_fft2muxf”NET“signal_u1 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u2 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u4 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u5 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u6 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u7 / u6 / u3 / u1 / Q1”register_duplication = {yes}; NET“signal_u8 / u6 / u3 / u1 / Q1“register_duplication = {yes}; NET”signal_u3 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u1 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u2 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u4 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u5 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET” signal_u6 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u7 / u6 / u3 / u1 / _add0000“register_duplication = {yes}; NET”signal_u8 / u6 / u3 / u1 / _add0000“register_duplication = {yes };结束 我得到了错误 Xst:1586 - 第4行:检测到语法错误第47列令牌为{。 检查您是否拼写错误的关键字(INST,NET,MODEL,...)或TIMESPEC标识符不以TS开头。 信号名称来自后映射静态时序报告。 非常感谢你! 以上来自于谷歌翻译 以下为原文 viviany wrote:This information is very useful. I also read in the XST user guide that one can set constraints in the XCF file whose syntax is BEGIN MODEL "entity_name" NET "signal_name" register_duplication={yes|no|true|false}; END; but if I use it as BEGIN MODEL "entity_fft2muxf" NET "signal_u1/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u2/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u4/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u5/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u6/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u7/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u8/u6/u3/u1/Q1" register_duplication={yes}; NET "signal_u3/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u1/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u2/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u4/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u5/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u6/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u7/u6/u3/u1/_add0000" register_duplication={yes}; NET "signal_u8/u6/u3/u1/_add0000" register_duplication={yes}; END I get the errors Xst:1586 - Line 4: Syntax error detected column 47 token is {. Check if you misspelled a keyword (INST, NET, MODEL, ...) or the TIMESPEC identifier does not begin with TS. The signal names are derived from post map static timing report. Thank you very much! |
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您不能在XCF中使用这些信号名称,因为这些信号来自综合后网表,而在合成之前使用XCF。
尝试在RTL代码中找到相应的信号,并使用XCF代码中的信号名称。 维维安 以上来自于谷歌翻译 以下为原文 You cannot use these signal names in XCF because these signal are from post-synthesis netlist while the XCF is used prior to syntheiszing. Try to find the corresponding signals in your RTL code and use the signal names in your code in XCF. Vivian |
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viviany写道:您不能在XCF中使用这些信号名称,因为这些信号来自综合后网表,而在合成之前使用XCF。
尝试在RTL代码中找到相应的信号,并使用XCF代码中的信号名称。 维维安 前8个信号NET“signal_u1 / u6 / u3 / u1 / Q1”register_duplication = {yes}; 与vhd文件中的相同,其余的似乎是29位加法运算的输出,XST可能会调用_add0000(只是一个猜测),但可能是在map之后,但它不应该显示第一个错误 8? 我成功实现了8个类似组件的一个组件,并且很好地满足了时序约束。 但是只要我用所有8个组件实现整体,我就先陷入物理综合,这仍然在继续,我可以在完成时提供更多信息,然后由于路由延迟而导致4 ns的松弛。 曾经完成了映射。 逻辑延迟可以忽略不计。 这很奇怪,因为在综合中我遇到的时钟是146 MHz而不是128 MHz的时钟,但在地图中,我被卡住了。 一条消息中的问题太多,对不起。 问候。 以上来自于谷歌翻译 以下为原文 viviany wrote:The first 8 signals NET "signal_u1/u6/u3/u1/Q1" register_duplication={yes}; are the same as in the vhd files and the rest seems to be the output of a 29 bit addition operation, which XST possibly calls _add0000 (just a guess) but may be that is after map but then it should not show errors for the first 8? Ihave successfully implemented one component of 8 similar ones and that met the timing constraint very well. But as soon as I implement the whole with all the 8 components, I get stuck first in physical synthesis, which is still continuing and I can provide more information when it completes and then I get a slack of 4 ns due to routing delays.I once had completed the mapping. Logic delays are negligible. This is strange since in synthesis I met the timing that is a clock of 146 MHz instead of 128 MHz but during map, I am stuck. Too many questions in one message, sorry for that. Regards. |
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以下是地图摘要。
设计没有使用完整的资源,但我仍然无法在地图中满足时间要求。 仅物理合成需要13个小时才能完成。 我只是使用了所示的设备,但是如果某些东西更合适,那么可以改变它。 设计信息------------------命令行:map -ise C:/virtex5_projects/fft2mux/fft2mux.ise -intstyle ise -p xc5vlx330t-ff1738-1 -w -logic_opt off-ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal off -cm speed -pr off-k 6 -lc off -bp -power off -o fft2muxf_map.ncd fft2muxf.ngd fft2muxf.pcf Target 设备:xc5vlx330tTarget包:ff1738目标速度:-1Mapper版本:virtex5 - $ Revision:1.46.12.2 $映射日期:星期五03月11日11:12:58 2009设计摘要--------------数字 错误:0警告数:414Slice逻辑利用率:切片寄存器数量:207,360中的50,013 24%用作触发器的数量:47,452用作锁存器的数量:2,561切片LUT数量:207,360中的62,333 30%用作逻辑的数字 :207,360中的30,535 14%仅使用O6输出的数字:21,658仅使用O5输出的数字:1,926使用O5和O6的数字:6,951用作内存的数字:54,71中的54,720 53%用作双端口RAM的数字:19,312 Numb 仅使用O6输出:18,960仅使用O5输出的数字:176使用O5和O6的数字:176用作单端口RAM的编号:176仅使用O6输出的编号:176用作移位寄存器的编号:10,013仅使用O6输出的编号:9,893 仅使用O5输出的数字:24使用O5和O6的数字:96用作独占路由的数字:2,297路由数量:414,720中的4,946 1%仅使用O6输出的数字:4,220仅使用O5输出的数字:726Slice Logic 分布:占用切片数量:51,840中的29,833 57%使用的LUT触发器数量:79,360未使用触发器的数量:79,360中的29,347 36%未使用的LUT数量:79,360中的17,027 21%完全数量 使用LUT-FF对:79,360中的32,986 41%独特控制集的数量:645控制集限制丢失的切片寄存器站点数量:207,360中的482 1%此架构的LUT触发器对代表一个LUT与一个LUT配对 翻转中的翻转翻转。 控制集是已注册元素的时钟,复位,设置和使能信号的唯一组合。 如果设计针对非切片资源进行过映射或放置失败,则切片逻辑分布报告无意义.IO利用率:绑定的IOB数量:960个中的309个32%IOB锁存器:161特定功能利用率:BlockRAM数量 / FIFO:168个中的168个51%仅使用BlockRAM的数量:168使用的总原语:使用的36k BlockRAM的数量:12使用的18k BlockRAM的数量:312使用的总内存(KB):11,664中的6,048 51%BUFG的数量/ BUFGCTRLs:32个中的16个50%用作BUFG的数量:16 DSP48E数量:192个中的160个83%峰值内存使用率:6568 MB总时间到MAP完成时间:15小时12分钟41秒完成MAP完成的总CPU时间:15 小时11分10秒 松弛是-3.704 ns 谢谢。 以上来自于谷歌翻译 以下为原文 Following is the map summary. The design is not using full resources but still I am not able to meet timing in the map. The physical synthesis alone took 13 hours to complete. I just used the device as shown but if something is more appropriate then can change to that. Design Information ------------------ Command Line : map -ise C:/virtex5_projects/fft2mux/fft2mux.ise -intstyle ise -p xc5vlx330t-ff1738-1 -w -logic_opt off -ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal off -cm speed -pr off -k 6 -lc off -bp -power off -o fft2muxf_map.ncd fft2muxf.ngd fft2muxf.pcf Target Device : xc5vlx330t Target Package : ff1738 Target Speed : -1 Mapper Version : virtex5 -- $Revision: 1.46.12.2 $ Mapped Date : Fri Apr 03 11:12:58 2009 Design Summary -------------- Number of errors: 0 Number of warnings: 414 Slice Logic Utilization: Number of Slice Registers: 50,013 out of 207,360 24% Number used as Flip Flops: 47,452 Number used as Latches: 2,561 Number of Slice LUTs: 62,333 out of 207,360 30% Number used as logic: 30,535 out of 207,360 14% Number using O6 output only: 21,658 Number using O5 output only: 1,926 Number using O5 and O6: 6,951 Number used as Memory: 29,501 out of 54,720 53% Number used as Dual Port RAM: 19,312 Number using O6 output only: 18,960 Number using O5 output only: 176 Number using O5 and O6: 176 Number used as Single Port RAM: 176 Number using O6 output only: 176 Number used as Shift Register: 10,013 Number using O6 output only: 9,893 Number using O5 output only: 24 Number using O5 and O6: 96 Number used as exclusive route-thru: 2,297 Number of route-thrus: 4,946 out of 414,720 1% Number using O6 output only: 4,220 Number using O5 output only: 726 Slice Logic Distribution: Number of occupied Slices: 29,833 out of 51,840 57% Number of LUT Flip Flop pairs used: 79,360 Number with an unused Flip Flop: 29,347 out of 79,360 36% Number with an unused LUT: 17,027 out of 79,360 21% Number of fully used LUT-FF pairs: 32,986 out of 79,360 41% Number of unique control sets: 645 Number of slice register sites lost to control set restrictions: 482 out of 207,360 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 309 out of 960 32% IOB Latches: 161 Specific Feature Utilization: Number of BlockRAM/FIFO: 168 out of 324 51% Number using BlockRAM only: 168 Total primitives used: Number of 36k BlockRAM used: 12 Number of 18k BlockRAM used: 312 Total Memory used (KB): 6,048 out of 11,664 51% Number of BUFG/BUFGCTRLs: 16 out of 32 50% Number used as BUFGs: 16 Number of DSP48Es: 160 out of 192 83% Peak Memory Usage: 6568 MB Total REAL time to MAP completion: 15 hrs 12 mins 41 secs Total CPU time to MAP completion: 15 hrs 11 mins 10 secs slack is -3.704 ns Thanks. |
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资源利用率报告对计时问题没有帮助。
您需要检查静态时序报告以查看它们的时序问题。 由于您使用的是大型设备(V5LX330T),因此15小时以上是合理的。 维维安 以上来自于谷歌翻译 以下为原文 Resources Utilization report does not help for timing issues. You need to check Static Timing Report to see what timing problems they are. Since you are using a large device (V5LX330T), 15+ hrs is reasonable. Vivian |
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对不起,我迟到了。
我能够达到8.537 ns的时间段代替7.812ns。 我将设备更改为vlx330速度等级-2因此我只滞后0.725 ns,我认为可以通过使用xplorer来实现。 但是一旦我启动xplorer,它就会在控制台中给出以下错误消息,它根本不会运行。 错误:无效的命令名称“getVersion”Xplorer运行失败。 然后我第二次运行它,然后它根本没有运行。 我已经运行这个项目3天,每次尝试不同的选项,现在我不想重新运行它,除非我没有其他办法。 如何让xplorer运行? 如果我更改xplorer的任何属性,那么这不会改变任何内容,仍然会检查实现图标。 非常感谢你。 消息由koyel.xilinx于04-07-2009 11:18 AM编辑 以上来自于谷歌翻译 以下为原文 Sorry for the late update. I am able to reach a time period of 8.537 ns in place of 7.812ns. I changed the device to vlx330 speed grade -2 so I am lagging by only 0.725 ns, which I think can be reached by using xplorer. But as soon as I start xplorer, it gives me following error message in the console and it doesn't run at all. ERROR: invalid command name "getVersion" Xplorer run failed. then I ran it second time and then it didn't run at all. I have been running this project for 3 days trying different options each time and now I do not want to rerun it unless I have no other way. How to make the xplorer run? If I change any property of xplorer then that doesn't change anything and still the implementation icon is checked. Thank you very much. Message Edited by koyel.xilinx on 04-07-2009 11:18 AM |
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你检查过这个AR http://www.xilinx.com/support/answers/31795.htm吗?
干杯, 吉姆 干杯,吉姆 以上来自于谷歌翻译 以下为原文 Have you checked this AR http://www.xilinx.com/support/answers/31795.htm? Cheers, Jim Cheers, Jim |
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我尝试了以下解决方案
解决方案1要解决此问题,请编辑ISE安装目录中的xplorer-lib.tcl脚本:Linux:$ XILINX / bin / scripts / xplorer-lib.tclWindows:%XILINX% bin scripts xplorer-lib.tcl1。 注释行号1704通过在行的开头加一个#来设置VERSION [getVersion $ VERSION]。 添加行集VERSION“10.1.03+(DEFAULT)”保存脚本并从GUI重新运行Xplorer。首先在我的tcl脚本中“set VERSION [getVersion $ VERSION]”不在第1704行,但我发现 并评论它。 要添加的行已经存在于文本开头的某处,但我再次在注释行的下方添加了该行。 我再次运行实现过程,因为这是我在调用xplorer之后通常所做的事情,但随后地图以交叉但没有错误的方式失败。 我已经更改了我的脚本,所以我不确定在地图失败后尝试使用秒数。 非常感谢你。 消息由koyel.xilinx于04-07-2009 03:03 PM编辑 以上来自于谷歌翻译 以下为原文 I have tried the following solution Solution 1 To work around the issue, edit the xplorer-lib.tcl script in the ISE install directory: Linux: $XILINX/bin/scripts/xplorer-lib.tcl Windows: %XILINX%binscriptsxplorer-lib.tcl 1. Comment out line number 1704 set VERSION [getVersion $VERSION] by putting a # at the start of the line. 2. Add line set VERSION "10.1.03+ (DEFAULT)" Save the script and re-run Xplorer from the GUI. First of all in my tcl script "set VERSION [getVersion $VERSION] " is not located in line 1704 but I found that and commented it. The line to be added is already there somewhere in the beginning of the text but I added that again just below the commented line. I ran the implementation process again as that is what I generally do after invoking xplorer but then the map failed with a cross but no errors. I have already changed my script so am not sure to try the second solution after map failed. Thank you very much. Message Edited by koyel.xilinx on 04-07-2009 03:03 PM |
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Xplorer错误是一个已知问题。
解决方案在AR 31795中提供:http://www.xilinx.com/support/answers/31795.htm 维维安 以上来自于谷歌翻译 以下为原文 The Xplorer error is an known issue. Solution is provided in AR 31795: http://www.xilinx.com/support/answers/31795.htm Vivian |
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没有xplorer就解决了这个问题。
之前我曾经过度限制了xcf文件,因为我在一些网站上发现了这些信息以满足时间要求,但在这种情况下,我通过不过度约束时间段来满足时间要求。 这很奇怪,虽然我认为我曾经尝试过正确的时期但可能有些选项不同,我不知道。 我认为SmartXplorer是下一次更好的选择。 感谢所有有价值的信息。 最好的祝福 以上来自于谷歌翻译 以下为原文 The problem is solved without xplorer. I had before overconstrained the xcf file as I found such information in some websites to meet timing but in this case I met the timing by NOT overconstraining the time period. This is strange though as I think I had tried before with the correct period but may be some options were different, which I am not aware of. I think SmartXplorer is a better option for the next time. Thanks for all the valuable information. Best Regards |
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