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嗨,
我正在使用vivado 2013.4并且在实现后从触发器的Q引脚到180个负载(RAMB36E1上的ENBWREN引脚)获得高扇出网络。 它符合时间,但是,我希望网络能够得到缓冲。 1.有没有办法确定哪些网络正在对它们进行扇出优化? 2.如果是,有没有办法确定为什么高扇出网没有得到优化? RAM原语包含在IP块(XCI)中,该块在合成期间变为黑盒子。 这可以解释为什么合成不会缓冲网络吗? 以上来自于谷歌翻译 以下为原文 Hi, I'm using vivado 2013.4 and am getting a high fanout net from the Q pin of a flop to 180 loads (ENBWREN pin on RAMB36E1) after implementation. It meets timing, however, I would've expected the net to get buffered. 1. Is there a way to determine which nets are getting fanout optimization performed on them? 2. If yes, is there a way to determine why high fanout nets don't get optimized? The RAM primitives are contained within an IP block (XCI) that gets black boxed during synthesis. Does that explain why synthesis isn't buffering the net? |
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嗨,
要确定是否执行了任何复制,请打开合成设计并搜索名称中包含* _rep *的单元格。 这些单元格是通过工具复制创建的,以减少扇出。 您是否在综合设置中使用MAX_FANOUT属性或将“fanout_limit”设置为其他值? -fanout_limit不影响控制信号(例如设置,复位,时钟使能)。 您需要使用MAX_FANOUT来复制这些信号。 fanout_limit也不是严格的限制。 此外,如果IP在上下文模式下合成,则复制可能不会像您所说的那样发生。 如果是这种情况,您可以在实现中使用place_design之后的phys_opt_design -force_replication_on_nets来减少特定网络的扇出。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, To find out if there is any replication performed, open synthesized design and search for cells which have *_rep* in their names. These cells are created by replication by tool to reduce the fanout. Are you using MAX_FANOUT attribute or setting "fanout_limit" to a different value in synthesis settings? -fanout_limit does not affect control signals (such as set, reset,clock enable). You need to use MAX_FANOUT to replicate these signals. Also fanout_limit is not a strict limit. Also if the IP is synthesized in out of context mode then the replication may not happen as you said. If that's the case, you can use phys_opt_design -force_replication_on_nets after place_design in implementation to reduce the fanout of specific nets. Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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我正在使用的策略将phys_opt_design -directive设置为AggressiveFanoutOpt。
该选项与-force_replication_on_nets选项有什么区别? 这些phys_opt_design选项是否仅作用于具有MAX_FANOUT属性的网络? 或者,它是时间驱动的吗? 以上来自于谷歌翻译 以下为原文 The strategy I'm using sets the phys_opt_design -directive to AggressiveFanoutOpt. What is the difference between that option and the -force_replication_on_nets option? Will these phys_opt_design options act on only the nets with MAX_FANOUT properties? Or, is it timing-driven? |
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在VHDL中添加MAX_FANOUT属性并设置为10之后,我重新运行了synthesis / impl,它仍然以180的扇出结束。它符合时序。
有人知道为什么合成可能无法满足MAX_FANOUT吗? 我在合成日志中收到此消息: 设计drfm_top有139个max_fanout违规无法满足 为什么它不能满足扇出违规? 此外,我正在启用phys_opt_design,甚至该步骤也没有做任何事情来降低扇出。 也许这可以解释为它没有看到MAX_FANOUT属性(我不确定它是否被传播到实现)并且没有任何时序问题,因此没有理由降低扇出。 以上来自于谷歌翻译 以下为原文 After adding a MAX_FANOUT attribute in the VHDL and set to 10, I re-ran through synthesis/impl and it still finishes with a fanout of 180. It meets timing. Does anybody know why synthesis might be unable to meet the MAX_FANOUT? I get this message in the synth log: design drfm_top has 139 max_fanout violations cannot be satisfied Why would it not be able to satisfy the fanout violations? Also, I'm enabling phys_opt_design and even that step doesn't do anything to lower the fanout. Perhaps that could be explained by it not seeing the MAX_FANOUT attribute (I'm not sure if that gets propogated to implementation) and not having any timing issues and thereforfe no reason to lower the fanout. |
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当为包含IP的设计运行合成时,工具会自动生成dont_touch.xdc,在合成IP期间在IP顶层设置DONT_TOUCH属性。
这可以防止删除接口端口。 因此,IP边界的扇出实际上是1,并且不会发生寄存器复制。 -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 When synthesis is run for a design containing IP, a dont_touch.xdc is automatically generated by tool, which sets DONT_TOUCH properties on the IP top-level during synthesis of the IP. This prevents interface ports from being removed. As a result, the fanout at the IP boundary is actually 1, and register replication doesn't occur.------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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如果网络扇出IP核的多个实例(.xci),该怎么办?
它是否将每个IP端口视为负载“1”并将其加起来,如果总数超过网络上的MAX_FANOUT属性,它是否会复制FF以减少扇出? 以上来自于谷歌翻译 以下为原文 What if a net fans out to multiple instances of the IP core (.xci). Does it view each IP port a load of "1" and add them up and if the total exceeds the MAX_FANOUT attribute on the net, will it then duplicate FFs to reduce the fanout? |
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好的,现在我看到我的网络在MAX_FANOUT为10的情况下被复制,因此它有10个负载,每个负载都是IP(XCI)。
在IP内部,还有额外的扇出,因此好像综合工具不知道IP内部的任何内容。 我想解决方案是将MAX_FANOUT预先缩放到较小的数字,以便考虑此工具限制。 以上来自于谷歌翻译 以下为原文 OK, now I'm seeing my net witht the MAX_FANOUT of 10 get replicated so that it has 10 loads, each of which is an IP (XCI). Inside the IP, there is additional fanout, so it is as if the synthesis tool is not aware of anything inside the IP. I guess the solution is to pre-scale the MAX_FANOUT to a lower number in order to account for this tool limitation. |
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