SPIS Rx中断问题

我使用两个PSoC 5LP有两个不同的草图。第一PSOC模拟一些SPI数据传输，第二个应该接收所有数据。RX缓冲区应该由DMA清除。SPIS-RX-IN被设置为“当FIFO不为空时中断”。问题是，从属只接收第一个字节（图片1）并且惯于重置RX中断（图片2）。我的草图是基于柏树的SPIM/SPIS-DMA例子。
8 = dma_tx_master
dma_rx_slave CH9 =
CH10 = spis_rx_interrupt
我也没有忘记一些SPI配置？
SPIS中断在第八时钟上升时是否正确？
是否有某种SPI连续接收模式？
workspace26_06m.cywrk.archive01.zip
563.4 K
workspace26_06s.cywrk.archive01.zip
604.5 K



     以下为原文
  I am using two PSoC 5LP with two different sketches. The first PSoC simulate some SPI-Data-Transfer and the second should receive all Data.
The RX-Buffer should be cleared by the DMA. The SPIS-Rx-Int. is set on "Interrupt when FIFO not Empty".
The problem is that the Slave only receive the first Byte (Picture 1) and wont reset the Rx Interrupt (Picture 2).
My Sketch based on the SPIM/SPIS-DMA example from cypress.

CH8= DMA_Tx_Master
CH9= DMA_Rx_Slave
CH10=SPIS_Rx_Interrupt

Did i forget some SPI config?
Is the timing for the SPIS-Interrupt correct at the 8th clock-rise?
Is there some kind of SPI-continously-receiving mode?

•   Workspace26_06M.cywrk.Archive01.zip 563.4 K
•   Workspace26_06S.cywrk.Archive01.zip 604.5 K