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我想用克隆的成分和修改它的cycontrolreg Verilog扩展组件的功能。我发现内容文件在这里,”PSoC Creator / 4.2/psoc创造者/ PSoC /内容/ cyprimitives / cyprimitives。cylib / cycontrolreg_v1_80”。如何复制/克隆/导出/????此组件,重命名它,修改它,然后用它在设计。我希望这不是一个新手的问题,但我试图找出发帖前。 谢谢, 克雷格 以上来自于百度翻译 以下为原文 Folks, I want to extend the functionality of the CyControlReg component by cloning the component and modifying it's verilog. I found the content files here, "PSoC Creator/4.2/PSoC Creator/psoc/content/CyPrimitives/CyPrimitives.cylib/CyControlReg_v1_80". How do I copy/clone/export/??? this component, rename it, modify it then use it in a design. I hope this isn't a newbie question but I did try to figure this out before posting here. Thanks, Craig |
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嗨,克雷格,
您可以通过以下步骤导入定制组件: 1。创建库项目/克隆/工作区中的出口; 2。将CyMeCurgV1.180组件从CyPrimId导入到创建的库; 三。右键单击您的工作区名称,选择依赖项对话框,在对话框中检查创建的库的“组件”和“代码”。 附件项目为FYI。 更多关于导出和导入组件的信息,您可以观看这些视频: HTTP://www. CyPress .COM/Primult/PSoC视频教程系列-HOW-CRATE定制组件 谢谢, 赖安 workspace39.cywrk.archive01.zip 602.7 K 以上来自于百度翻译 以下为原文 Hi Craig, You could import the customized component with following steps: 1. Create a Library project in /clone/export in your workspace; 2. Import CyControlReg_v1_80 Component from Cyprimitives to the created library; 3. Right-click on your workspace name, select Dependencies dialog, check 'Components' and 'Code' of the created library in the dialog. Attached project is FYI. More information about export and import component, you could watch these videos: http://www.cypress.com/training/psoc-video-tutorial-series-how-create-custom-components Thanks, Ryan
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赖安 感谢视频链接。昨天我试着在YouTube上看这些,但是我无法确定这个系列中的顺序或是多少。有没有一个播放列表,他们或者他们的编号。别担心。 所以我看你发送的链接,我可以看到我错过了一些。今天晚上我会按照正确的顺序重温这些,然后按照上面的步骤进行。 谢谢, 克雷格 以上来自于百度翻译 以下为原文 Ryan, Thanks for the videos link. I tried to watch these on YouTube yesterday but I couldn't figure out the order or how many were in the series. There's not a playlist for them or are they numbered. No worries. So I looking the link you sent, I can see that I missed some. I'll rewatch these this evening in the correct order, then follow the step above. Thanks, Craig |
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赖安 我能够创造一个图书馆和进口cycontrolreg你概述了上面的步骤。我很快就发现cycontrolreg实施远比我以为的要复杂得多。看起来像是一个完美的机会去了解更多的关于PSoC组件开发。谢谢你的解决方案。 克雷格 以上来自于百度翻译 以下为原文 Ryan, I was able to create a library and import the CyControlReg as you outlined in the steps above. I quickly discovered CyControlReg implementation is far more complicated than I assumed. Looks like it a perfect opportunity to learn more about PSoC component development. Thanks for the solution. Craig |
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60user69 发表于 2018-8-19 00:54 克雷格 你想加入CREG什么功能? ODISSEY1 以上来自于百度翻译 以下为原文 Craig, what functionality you want to add to CReg? /odissey1 |
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我正在一个数控项目控制步进电机。一些汽车司机要设置时间如果方向信号的变化,在接受一个阶跃信号,像50us。我想,CREG MOD可能把这延迟的硬件。 以上来自于百度翻译 以下为原文 I'm working a CNC project to control stepper motors. Some motor drivers want a setup time if direction signal changes before accepting a step signal, like 50uS. I figured CReg mod could add this delay in hardware. |
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60user69 发表于 2018-8-19 01:23 克雷格 一些解决方案是可能的(和W/O CREG),这取决于所需的50'延迟的准确性。我猜你想在代码中写1到一个输出引脚,然后把PIN放到50Us后面。 1。使用DFF(触发器)后,CReg,连接到20kHz时钟。单个DFF脉冲延迟将变化0~50US。两个DFF系列和10kHz时钟延迟25-50US,等等更多的DFFS -更好的精度。CREG可以作为单一的DFF如果配置同步模式。 2。可以使用SHIVESTRIGSTER组件,8BIIT模式(不需要CREG)。只需写移位寄存器值,输出信号将延迟8个时钟。 三。使用单镜头模式定时器。脉冲延迟可以通过计数器基和时钟控制。 4。使用count7在单发模式计数器。 5。使用DMA和环形缓冲延迟写入资料。延迟时间则是指由缓冲区长度和DMA时钟。 张贴链接到控制器的数据将是有益的。 ODISSEY1 以上来自于百度翻译 以下为原文 Craig, Several solutions are possible (with and w/o CReg), depending on the required accuracy of the '50us' delay. I guess that you want to write 1 to an output pin in the code and have pin to go UP 50us later. 1. Use DFF (flip-flop) after CReg, attached to 20kHz clock. Single DFF pulse delay will vary 0-50us. Two DFFs in series and 10kHz clock yield delay 25-50us, etc. More DFFs - better accuracy. The CReg can act as single DFF if configured in Sync mode. 2. Can use a ShiftRegister component, 8-biit mode (no CReg required). Just write Shift register value, and the output signal will be delayed by 8 clocks. 3. Using Timer in single-shot mode. The pulse delay can be controlled by counter base and clock. 4. Using Count7 down counter in single-shot mode. 5. Using DMA and circular buffer to delay data written to a pin. Delay time then is defined by buffer length and DMA clock. Posting a link to the controller datasheet would be helpful. /odissey1 |
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nvwuwy 发表于 2018-8-19 01:30 ODISSEY1 感谢所有这些想法。我应该把这个项目公布出来。我正在帮助Bart Dring使用GRBL端口到PSoC5,GITHUB-BDRIG/GRBLISUBSUTION:一个带有本地USB支持的GSOBL端口 如果你把他的项目打开到TopDebug /步进器,你会看到FieldReGig步骤(它有一个脉冲输出)和CopyReGuiDIR。他只希望在DIR输出改变后DIR输出时延迟步进脉冲。 我会更多地考虑你的评论,并试图找出一个简单的解决方案。 克雷格 以上来自于百度翻译 以下为原文 Odissey1, Thanks for all these ideas. I should have posted the project. I'm helping Bart Dring with his grbl port to PSoC5, GitHub - bdring/Grbl_USB_Native: A PSoC5 port of Grbl with native USB support If you open his project to TopDesign/Steppers, you'll see Control_Reg_Step (which is has a pulse output) and Control_Reg_Dir. He wants to delay the step pulse only if dir output after dir output changes. I'll think more about your comments and try to figure out a simple solution. Craig |
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