请教 关于6678 PLL 的一点疑问

大家好
在文档 sprugv2f  3.1.1 Initialization to PLL Mode里面描述了配置PLL的过程
我对第2、3步有点疑问，原文如下
"
2. Check the status of BYPASS bit in SECCTL register, execute following steps if
BYPASS == 1 (if bypass enabled), if BYPASS == 0 then Jump to Step 3
a. In MAINPLLCTL1, write ENSAT = 1 (for optimal PLL operation)
b. In PLLCTL, write PLLEN = 0 (bypass enabled in PLL Controller mux)
c. In PLLCTL, write PLLENSRC = 0 (enable PLLEN to control PLL Controller
mux)
d. Wait 4 cycles of the reference clock CLKIN (to make sure the PLL Controller
mux switches properly to the bypass)
e. In SECCTL, write BYPASS = 1 (bypass enabled in PLL mux)
f. In PLLCTL, write PLLPWRDN = 1 (power down the PLL)
g. Wait for at least 5 μs based on the reference clock CLKIN (PLL power down
toggling time)
h. In PLLCTL, write PLLPWRDN = 0 (power up the PLL. Jump to Step 4
3. Enable BYPASS in the PLL Controller
a. In PLLCTL, write PLLEN = 0 (bypass enabled in PLL Controller mux)
b. In PLLCTL, write PLLENSRC = 0 (enable PLLEN to control PLL Controller
mux)
"
这里我的疑问是，根据上文，BYPASS == 1的时候执行步骤2，BYPASS == 0的时候执行步骤3
可在步骤2里面有e项再次执行了将BYPASS置1的操作，而步骤3里面没有对BYPASS进行操作。
所以我理解这样执行的结果是，经过2或3的步骤之后，BYPASS的值会保持不变，即执行前是0或1，
执行之后也依旧是0或1。
由于手头的板卡还没有制板完毕，所以还仅仅是停留在文档的角度，没有实际尝试。
请问我这么理解有什么问题吗？

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另外就是我觉得 Table 4-3 PLL Secondary Control Register (SECCTL) Field Descriptions 里面有一点错误，
OUTPUT DIVIDE的描述里面的最后一句，4h - Fh = ÷5 to ÷16. Divide frequency by 5 to divide frequency by 80.
最后是否应该是16而不是80.