cc1310的巴伦滤波电路电容电感选0.1%的还是1%的？

TI的原则是选品牌型号完全一致的, 比如Balun电路,可能利用了器件的高频特性,这是从成本考量的. 不能只是选值的大小一致.
TI的任何参考设计都提供了完整的BOM, BOM中描述了器件的型号,品牌等.
请参考TI文档:
http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=swra367a&keyMatch=review&tisearch=Search-EN-Everything
其中的关键原则如下(第4章):
4 Copying TI Reference Design The first step to start a RF PCB layout is to understand the PCB board properties, i.e. the PCB stack-up and dielectric properties (dielectric constant and loss tangent). TI reference designs include a document describing PCB board stack-up and board properties such as stacking heights, dielectric constant and loss tangent of the board’s dielectric. Check the TI reference design-specified board parameters and confirm with your board manufacturer if you can use these recommended specifications. If not, then refer to the application note AN068 [2] on how to adapt the reference designs for the board stack-up changes. Then copy the schematic and layout as closely as possible.
Also, if the design requires translating a two-layer TI reference design to a four-layer PCB design, then the height between the top layer and ground plane may change. This changes the impedance of the RF path. The change in the impedance in the RF path must be accounted for by adjusting the widths of the traces as explained in the application note AN068 [2].
Additionally, to make it easier to copy the reference designs, many TI reference designs includes a white box silkscreen that shows the extent of RF layout. Everything inside the box should be copied exactly for optimum performance. Anything outside the box can be changed freely.
The checklist below provides important RF PCB design considerations to be followed, and it is highly recommended that the designers verify their designs with the suggested points below. Following these points in the checklist will help to achieve optimum performance from the designs.
1 Ensure that you follow the datasheet layout recommendation unique to the part (CCXXXX).
2 0603(mils) discrete parts are not recommended because of size and parasitic values.
3 Verify that bypassing capacitors are as close as possible to the power supply pins that they are meant to bypass.
4 Ensure each decoupling capacitor only decouples the specific pins recommended on the reference design and that the capacitor is correct value and type.
5 Ensure that decoupling is done pin<>capacitor<>via.
6 Verify the stack-up matches the reference design. If the design is a 4-layer PCB; verify that ground plane is layer two right below top/component side.
7 Changing the layer spacing/stack-up will affect the matching in the RF signal path and should be carefully accounted for as explained in AN068 [2].
8 Verify that the ground plane matches the reference design. There should be a solid ground plane below the device and the RF path. There should be no ground plane below the antenna unless you are using an antenna whose manufacturer recommends a ground plane (for example, a whip antenna).
9 Verify that RF signal path matches the reference design as closely as possible. Components should be arranged in a very similar way and oriented the same way as the reference design.
10 The crystal oscillator should be as close as possible to the oscillator pins of the part. Long lines to the oscillator should be avoided if possible.
11 Verify that the top ground pours are stitched to the ground plane layer and bottom layer with many vias around the RF signal path. Compare to the reference design. Vias on the rest of the board should be no more than λ/10 apart.
12 If the part has a differential output, ensure that the traces in the differential section are symmetrical as in the reference design.
13 If the design uses a battery (such as a coin cell), the battery will act as a ground plane and should therefore not be placed under the antenna.
14 If the reference design specifies using T-Lines (Transmission Lines), it is very critical to ensure that the T-Lines match the reference design exactly.
15 Verify that the under-the-device power pad layout is correct. The solder pads and mask should match and the opening size should ensure correct amount of paste. Vias should be the correct number and masked/tented to ensure that they don’t suck up all the solder, leaving none to solder the chip to pad. (Refer to the datasheet for layout recommendation for the corresponding part.)
16 The board should specify impedance controlled traces. That is, the layer spacing and FR4 permittivity should be controlled and known.