C6657 CSL 与手册对应问题（TMR)

C6657手册中 的 TCR ENAMODE_ LO 描述如下
Enabling mode bits determine the timer mode.
00b = The timer is disabled (not counting) and maintains the current value.
01b = The timer is enabled one time. The timer stops after the timer counter reaches the timer period.
10b = The timer is enabled continuously. The timer counter increments until it reaches the timer period. One
timer clock cycle later, the timer counter is reset to 0 and continues counting.
11b = The timer is enabled continuously. The timer counter increments until it reaches the timer period. One
timer clock cycle later, the timer counter is reset to 0, the period registers (PRDHI and PRDLO) reload with the
reload registers (RELHI and RELLO) and continues counting when TIMMODE is either set to 00b (64-bit timer
mode) or 01b (32-bit timers unchained mode).
可是 CSL 中之定义到2！是我理解有问题，还是这个库文件有问题！
typedef enum [
/** The timer is disabled and maintains current value */
CSL_TMR_ENAMODE_DISABLE = 0,
/** The timer is enabled one time */
CSL_TMR_ENAMODE_ENABLE = 1,
/** The timer is enabled continuously */
CSL_TMR_ENAMODE_CONT = 2
] CSL_TmrEnamode;