请问有什么办法可以改变28035CLA内存吗？使得内存中可以放置更多的数组？

F28035的CLA的数据RAM和程序RAM是固定大小的，请参考memory map进行分配和使用。
                                                                         If a post answers your question, please mark it with the "verify answer" button.

 你好，为什么查看.map还是有剩余的，但是就是不运行？

你这样问我不知道怎么回答你，因为我不知道你使用了哪个RAM区，没看到你的.map，也不知道你的CLA里内存是如何配置的。
如果需要深究，请提供更多详细的信息才能帮你分析。
                                                                         If a post answers your question, please mark it with the "verify answer" button.

一、变量定义：
typedef struct [
int vector;
float Uab; //ab电压
float Uca; //ac电压
float Ucb; //bc电压
float Uabold[5];
float Ucaold[5];
float Ucbold[5];
float Uref;
float Ia; //a电流
float Ib; //b电流
float Ic; //c电流
float PCBTemperature; //控制板温度
float Udhis[180];
float Uqhis[180];
]AD_REG;
#define AD_DEFAULTS [0,0,0,0,0,0,0,0,0,0,0,0,0,0]
二、CLA.C文件
/*
* adc.h
*
*
Created on: 2016-11-22
Author : ZHANGZIYING
*
*
*/
#include "DSP28x_Project.h" // DSP28x Headerfile
#include "DSP2803x_Cla_defines.h"
#include "cla.h"
#pragma DATA_SECTION(ad,"Cla1DataRam0")
AD_REG ad = AD_DEFAULTS;
#pragma DATA_SECTION(state,"Cla1DataRam0")
STATE_REG state = STATE_DEFAULTS;
#pragma DATA_SECTION(index,"Cla1DataRam0")
Uint16 index = 0;
#pragma DATA_SECTION(PCBTemperature,"Cla1ToCpuMsgRAM")
float PCBTemperature = 0;
#pragma DATA_SECTION(Uab,"Cla1ToCpuMsgRAM")
float Uab = 0;
#pragma DATA_SECTION(Ubc,"Cla1ToCpuMsgRAM")
float Ubc = 0;
#pragma DATA_SECTION(Uca,"Cla1ToCpuMsgRAM")
float Uca = 0;
#pragma DATA_SECTION(Ia,"Cla1ToCpuMsgRAM")
float Ia = 0;
#pragma DATA_SECTION(Ib,"Cla1ToCpuMsgRAM")
float Ib = 0;
#pragma DATA_SECTION(Ic,"Cla1ToCpuMsgRAM")
float Ic = 0;
#pragma DATA_SECTION(Period,"CpuToCla1MsgRAM")
float Period = 0;
#pragma DATA_SECTION(grid_alpha,"Cla1ToCpuMsgRAM")
float grid_alpha = 0;
#pragma DATA_SECTION(RunEnableFlag,"CpuToCla1MsgRAM")
Uint16 RunEnableFlag = 0;
#pragma DATA_SECTION(lock_flag,"Cla1ToCpuMsgRAM")
Uint16 lock_flag = 0;
#pragma DATA_SECTION(postive_negetive_flag,"Cla1ToCpuMsgRAM")
Uint16 postive_negetive_flag = 0;
#pragma DATA_SECTION(cnt,"Cla1DataRam0")
Uint16 cnt = 0;
#pragma DATA_SECTION(Ud,"Cla1DataRam0")
float Ud = 0;
#pragma DATA_SECTION(Uq,"Cla1DataRam0")
float Uq = 0;
#pragma DATA_SECTION(Udfil,"Cla1DataRam0")
float Udfil = 0;
#pragma DATA_SECTION(Uqfil,"Cla1DataRam0")
float Uqfil = 0;
/*
#pragma DATA_SECTION(Udhis,"Cla1DataRam0") //这样定义有问题，数据过大，CLA不运行，所以定义改在AD结构体中，具体原因不详，注意！！！
float Udhis[100] = [0];
#pragma DATA_SECTION(Uqhis,"Cla1DataRam0")
float Uqhis[100] =[0];
*/
void ConfigCla(void)
[
/* Assign user defined ISR to the PIE vector table */
EALLOW;
//PieVectTable.CLA1_INT1 = &cla1_task1_isr;
//PieVectTable.CLA1_INT2 = &cla1_task2_isr;
//PieVectTable.CLA1_INT3 = &cla1_task3_isr;
// PieVectTable.CLA1_INT4 = &cla1_task4_isr;
//PieVectTable.CLA1_INT5 = &cla1_task5_isr;
//PieVectTable.CLA1_INT6 = &cla1_task6_isr;
//PieVectTable.CLA1_INT7 = &cla1_task7_isr;
PieVectTable.CLA1_INT8 = &cla1_task8_isr;
EDIS;
//Copy over the CLA code and Tables
memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);
memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);
/* Compute all CLA task vectors */
EALLOW;
//Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 - (Uint32)&Cla1Prog_Start);
//Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 - (Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 - (Uint32)&Cla1Prog_Start);
EDIS;
// Mapping CLA tasks
/* All tasks are enabled and will be started by an ePWM trigger
* Map CLA program memory to the CLA and enable software breakpoints
*/
EALLOW;
//Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_EPWM1INT; //CLA_INT1_ADCINT1 work seccessfully
//Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_ADCINT1; ;
//Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;
//Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_EPWM4INT;
//Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;
//Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;
//Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_CPUTIMER0INT;
Cla1Regs.MIER.bit.INT8 = 1; //Task8 interrupt is enabled
EDIS;
/* Enable CLA interrupts at the group and subgroup levels */
PieCtrlRegs.PIEIER11.bit.INTx8 = 1;
IER = (M_INT11 );
/* Switch the CLA program space to the CLA and enable software forcing
* Also switch over CLA data ram 0 and 1
*/
EALLOW;
Cla1Regs.MMEMCFG.bit.PROGE = 1; //一旦存储器被 CLA 代码初始化，主 CPU 就通过写 1 到 MMEMCFG[PROGE]位将其映射到 CLA 程序空间
Cla1Regs.MCTL.bit.IACKE = 1; //Enable the instruction (IACK #0x0001: Write a 1 to MIFRC bit 0 to force task 1)
Cla1Regs.MMEMCFG.bit.RAM0E = CLARAM0_ENABLE; //一旦存储器被 CLA 代码初始化，主 CPU 就将其映射到 CLA 空间。两个存储块可以分别通过 MMEMCFG[RAM0E]和 MMEMCFG[RAM1E]位被映射
Cla1Regs.MMEMCFG.bit.RAM1E = CLARAM1_ENABLE;
EDIS;
]
//###########################################################################
// CLA ISRs
//###########################################################################
__interrupt void cla1_task8_isr( void)
[
PieCtrlRegs.PIEACK.bit.ACK11 = 1;
]
三、F28035_CLA_C.cmd文件
/*
//###########################################################################
//
// FILE: F28035_CLA_C.cmd
//
// TITLE: Linker Command File For F28035 Device
//
//###########################################################################
// $TI Release: F2803x C/C++ Header Files and Peripheral Examples V128 $
// $Release Date: March 30, 2013 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in DSP2803x_Headerscmd
//
// For BIOS applications add: DSP2803x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2803x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2803x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2803x_Headers_BIOS.cmd */
/* 2) In your project add the path to DSP2803x_headerscmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28035
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2803x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x200
-stack 0x200
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
[
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
CLARAM0 : origin = 0x008800, length = 0x000800
// CLARAM1 : origin = 0x008C00, length = 0x000400
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080

FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
]
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
[
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHC PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAMM0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.cio : > RAML0 PAGE = 1
.sysmem : > RAMM1 PAGE = 1
.ebss : > RAML0 PAGE = 1
.esysmem : > RAML0 PAGE = 1

/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0

/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD

.bss_cla : > CLARAM0, PAGE = 1

Cla1Prog : LOAD = FLASHE,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > CLARAM0, PAGE = 1
// Cla1DataRam1 : > CLARAM1, PAGE = 1

GROUP : LOAD = FLASHB,
RUN = CLARAM0,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
RUN_START(_Cla1mathTablesRunStart),
LOAD_SIZE(_Cla1mathTablesLoadSize),
PAGE = 1

[
CLA1mathTables
.const_cla
]

CLAscratch :
[ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) ] > CLARAM0,
PAGE = 1

/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
[
IQmath.lib (IQmathTablesRam)
]
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
[
IQmath.lib (IQmathTablesRam)
]
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
]
/*
//===========================================================================
// End of file.
//===========================================================================
*/
四、.map文件
******************************************************************************
TMS320C2000 Linker PC v6.1.0
******************************************************************************
>> Linked Wed Dec 28 20:23:12 2016
OUTPUT FILE NAME:
ENTRY POINT SYMBOL: "_c_int00" address: 003f325b

MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
RAMM0 00000050 000003b0 00000021 0000038f RWIX
RAML3 00009000 00001000 00000670 00000990 RWIX
OTP 003d7800 00000400 00000000 00000400 RWIX
FLASHH 003e8000 00002000 00000000 00002000 RWIX
FLASHG 003ea000 00002000 00000000 00002000 RWIX
FLASHF 003ec000 00002000 00000000 00002000 RWIX
FLASHE 003ee000 00002000 00000670 00001990 RWIX
FLASHD 003f0000 00002000 00000021 00001fdf RWIX
FLASHC 003f2000 00002000 000015a8 00000a58 RWIX
FLASHA 003f6000 00001f80 00000595 000019eb RWIX
CSM_RSVD 003f7f80 00000076 00000000 00000076 RWIX
BEGIN 003f7ff6 00000002 00000002 00000000 RWIX
CSM_PWL_P0 003f7ff8 00000008 00000000 00000008 RWIX
IQTABLES 003fe000 00000b50 00000b50 00000000 RWIX
IQTABLES2 003feb50 0000008c 00000000 0000008c RWIX
IQTABLES3 003febdc 000000aa 00000000 000000aa RWIX
ROM 003ff27c 00000d44 00000000 00000d44 RWIX
RESET 003fffc0 00000002 00000000 00000002 RWIX
VECTORS 003fffc2 0000003e 00000000 0000003e RWIX
PAGE 1:
BOOT_RSVD 00000000 00000050 00000000 00000050 RWIX
RAMM1 00000400 00000400 00000200 00000200 RWIX
DEV_EMU 00000880 00000105 00000004 00000101 RWIX
SYS_PWR_CTL 00000985 00000003 00000003 00000000 RWIX
FLASH_REGS 00000a80 00000060 00000008 00000058 RWIX
CSM 00000ae0 00000010 00000010 00000000 RWIX
ADC_RESULT 00000b00 00000020 00000020 00000000 RWIX
CPU_TIMER0 00000c00 00000008 00000008 00000000 RWIX
CPU_TIMER1 00000c08 00000008 00000008 00000000 RWIX
CPU_TIMER2 00000c10 00000008 00000008 00000000 RWIX
PIE_CTRL 00000ce0 00000020 0000001a 00000006 RWIX
PIE_VECT 00000d00 00000100 00000100 00000000 RWIX
CLA1 00001400 00000080 00000040 00000040 RWIX
CLA1_MSGRAMLOW 00001480 00000080 00000012 0000006e RWIX
CLA1_MSGRAMHIGH 00001500 00000080 00000004 0000007c RWIX
ECANA 00006000 00000040 00000034 0000000c RWIX
ECANA_LAM 00006040 00000040 00000040 00000000 RWIX
ECANA_MOTS 00006080 00000040 00000040 00000000 RWIX
ECANA_MOTO 000060c0 00000040 00000040 00000000 RWIX
ECANA_MBOX 00006100 00000100 00000100 00000000 RWIX
COMP1 00006400 00000020 00000014 0000000c RWIX
COMP2 00006420 00000020 00000014 0000000c RWIX
COMP3 00006440 00000020 00000014 0000000c RWIX
EPWM1 00006800 00000040 00000040 00000000 RWIX
EPWM2 00006840 00000040 00000040 00000000 RWIX
EPWM3 00006880 00000040 00000040 00000000 RWIX
EPWM4 000068c0 00000040 00000040 00000000 RWIX
EPWM5 00006900 00000040 00000040 00000000 RWIX
EPWM6 00006940 00000040 00000040 00000000 RWIX
EPWM7 00006980 00000040 00000040 00000000 RWIX
ECAP1 00006a00 00000020 00000020 00000000 RWIX
HRCAP1 00006ac0 00000020 00000020 00000000 RWIX
HRCAP2 00006ae0 00000020 00000020 00000000 RWIX
EQEP1 00006b00 00000040 00000040 00000000 RWIX
LINA 00006c00 00000080 0000004a 00000036 RWIX
GPIOCTRL 00006f80 00000040 00000040 00000000 RWIX
GPIODAT 00006fc0 00000020 00000020 00000000 RWIX
GPIOINT 00006fe0 00000020 0000000c 00000014 RWIX
SYSTEM 00007010 00000020 00000020 00000000 RWIX
SPIA 00007040 00000010 00000010 00000000 RWIX
SCIA 00007050 00000010 00000010 00000000 RWIX
NMIINTRUPT 00007060 00000010 00000010 00000000 RWIX
XINTRUPT 00007070 00000010 00000010 00000000 RWIX
ADC 00007100 00000080 00000050 00000030 RWIX
SPIB 00007740 00000010 00000010 00000000 RWIX
I2CA 00007900 00000040 00000022 0000001e RWIX
RAML0 00008000 00000800 00000244 000005bc RWIX
CLARAM0 00008800 00000800 0000066c 00000194 RWIX
PARTID 003d7e80 00000001 00000001 00000000 RWIX
FLASHB 003f4000 00002000 00000228 00001dd8 RWIX
CSM_PWL 003f7ff8 00000008 00000008 00000000 RWIX

SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.pinit 0 003f6000 00000000 UNINITIALIZED
Cla1Prog 0 003ee000 00000670 RUN ADDR = 00009000
003ee000 00000300 sample.obj (Cla1Prog:retain)
003ee300 00000262 sample.obj (Cla1Prog)
003ee562 00000040 CLAlog10.obj (Cla1Prog)
003ee5a2 0000003a CLAmath.lib : CLAcos.obj (Cla1Prog)
003ee5dc 0000003a : CLAln.obj (Cla1Prog)
003ee616 0000003a : CLAsin.obj (Cla1Prog)
003ee650 00000020 : CLAsqrt.obj (Cla1Prog)
ramfuncs 0 003f0000 00000021 RUN ADDR = 00000050
003f0000 0000001d DSP2803x_SysCtrl.obj (ramfuncs)
003f001d 00000004 DSP2803x_usDelay.obj (ramfuncs)
.text 0 003f2000 000015a8
003f2000 000003d7 modbus.obj (.text)
003f23d7 000002f4 protec_state.obj (.text)
003f26cb 000001c3 epwm.obj (.text)
003f288e 000001a9 DSP2803x_Adc.obj (.text)
003f2a37 0000017c DSP2803x_DefaultIsr.obj (.text:retain)
003f2bb3 00000146 DSP2803x_SysCtrl.obj (.text)
003f2cf9 000000ec DSP2803x_EPwm.obj (.text)
003f2de5 0000008f adc.obj (.text)
003f2e74 00000083 rts2800_ml.lib : fd_mpy.obj (.text)
003f2ef7 00000083 : fs_div.obj (.text)
003f2f7a 0000007b DSP2803x_ECan.obj (.text)
003f2ff5 00000078 rts2800_ml.lib : fs_add.obj (.text)
003f306d 00000073 gpio.obj (.text)
003f30e0 0000005a rts2800_ml.lib : fs_mpy.obj (.text)
003f313a 0000004b cla.obj (.text)
003f3185 0000004a ecap.obj (.text)
003f31cf 00000047 sci.obj (.text)
003f3216 00000045 main.obj (.text)
003f325b 00000044 rts2800_ml.lib : boot.obj (.text)
003f329f 0000003b DSP2803x_CpuTimers.obj (.text)
003f32da 0000002c ecap.obj (.text:retain)
003f3306 00000029 rts2800_ml.lib : fs_tol.obj (.text)
003f332f 00000028 DSP2803x_PieCtrl.obj (.text)
003f3357 00000027 epwm.obj (.text:retain)
003f337e 00000025 rts2800_ml.lib : fs_toi.obj (.text)
003f33a3 00000023 timer.obj (.text)
003f33c6 00000021 timer.obj (.text:retain)
003f33e7 00000021 rts2800_ml.lib : fs_toul.obj (.text)
003f3408 00000021 : memcpy_ff.obj (.text)
003f3429 0000001f : fd_tol.obj (.text)
003f3448 0000001d : i_tofd.obj (.text)
003f3465 0000001c DSP2803x_Sci.obj (.text)
003f3481 0000001c rts2800_ml.lib : fs_tofd.obj (.text)
003f349d 0000001a : l_tofs.obj (.text)
003f34b7 00000019 : args_main.obj (.text)
003f34d0 00000019 : exit.obj (.text)
003f34e9 00000019 : prolog.obj (.text)
003f3502 00000017 crc.obj (.text)
003f3519 00000017 rts2800_ml.lib : fs_cmp.obj (.text)
003f3530 00000014 DSP2803x_ECap.obj (.text)
003f3544 00000013 DSP2803x_Gpio.obj (.text)
003f3557 00000013 rts2800_ml.lib : ul_tofs.obj (.text)
003f356a 00000011 DSP2803x_PieVect.obj (.text)
003f357b 0000000c rts2800_ml.lib : epilog.obj (.text)
003f3587 00000009 cla.obj (.text:retain)
003f3590 00000009 rts2800_ml.lib : _lock.obj (.text)
003f3599 00000008 DSP2803x_CodeStartBranch.obj (.text)
003f35a1 00000007 DSP2803x_DisInt.obj (.text)
.econst 0 003f6000 00000304
003f6000 00000100 DSP2803x_PieVect.obj (.econst)
003f6100 00000100 crc.obj (.econst:_auchCRCHi)
003f6200 00000100 crc.obj (.econst:_auchCRCLo)
003f6300 00000004 modbus.obj (.econst)
.cinit 0 003f6304 00000236
003f6304 000000c9 protec_state.obj (.cinit)
003f63cd 00000097 cla.obj (.cinit)
003f6464 00000089 modbus.obj (.cinit)
003f64ed 00000020 pwm_run_stop.obj (.cinit)
003f650d 0000000d epwm.obj (.cinit)
003f651a 0000000a rts2800_ml.lib : _lock.obj (.cinit)
003f6524 0000000a : exit.obj (.cinit)
003f652e 00000005 main.obj (.cinit)
003f6533 00000005 timer.obj (.cinit)
003f6538 00000002 --HOLE-- [fill = 0]
IQmath 0 003f653a 0000005b
003f653a 00000047 IQmath.lib : IQ10div.obj (IQmath)
003f6581 00000014 : IQ10toF.obj (IQmath)
codestart
* 0 003f7ff6 00000002
003f7ff6 00000002 DSP2803x_CodeStartBranch.obj (codestart)
IQmathTables
* 0 003fe000 00000b50 NOLOAD SECTION
003fe000 00000b50 IQmath.lib : IQmathTables.obj (IQmathTables)
.reset 0 003fffc0 00000002 DSECT
003fffc0 00000002 rts2800_ml.lib : boot.obj (.reset)
vectors 0 003fffc2 00000000 DSECT
.stack 1 00000400 00000200 UNINITIALIZED
00000400 00000200 --HOLE--
DevEmuRegsFile
* 1 00000880 00000004 UNINITIALIZED
00000880 00000004 DSP2803x_GlobalVariableDefs.obj (DevEmuRegsFile)
SysPwrCtrlRegsFile
* 1 00000985 00000003 UNINITIALIZED
00000985 00000003 DSP2803x_GlobalVariableDefs.obj (SysPwrCtrlRegsFile)
FlashRegsFile
* 1 00000a80 00000008 UNINITIALIZED
00000a80 00000008 DSP2803x_GlobalVariableDefs.obj (FlashRegsFile)
CsmRegsFile
* 1 00000ae0 00000010 UNINITIALIZED
00000ae0 00000010 DSP2803x_GlobalVariableDefs.obj (CsmRegsFile)
AdcResultFile
* 1 00000b00 00000020 UNINITIALIZED
00000b00 00000020 DSP2803x_GlobalVariableDefs.obj (AdcResultFile)
CpuTimer0RegsFile
* 1 00000c00 00000008 UNINITIALIZED
00000c00 00000008 DSP2803x_GlobalVariableDefs.obj (CpuTimer0RegsFile)
CpuTimer1RegsFile
* 1 00000c08 00000008 UNINITIALIZED
00000c08 00000008 DSP2803x_GlobalVariableDefs.obj (CpuTimer1RegsFile)
CpuTimer2RegsFile
* 1 00000c10 00000008 UNINITIALIZED
00000c10 00000008 DSP2803x_GlobalVariableDefs.obj (CpuTimer2RegsFile)
PieCtrlRegsFile
* 1 00000ce0 0000001a UNINITIALIZED
00000ce0 0000001a DSP2803x_GlobalVariableDefs.obj (PieCtrlRegsFile)
PieVectTableFile
* 1 00000d00 00000100 UNINITIALIZED
00000d00 00000100 DSP2803x_GlobalVariableDefs.obj (PieVectTableFile)
EmuKeyVar
* 1 00000d00 00000001 UNINITIALIZED
00000d00 00000001 DSP2803x_GlobalVariableDefs.obj (EmuKeyVar)
EmuBModeVar
* 1 00000d01 00000001 UNINITIALIZED
00000d01 00000001 DSP2803x_GlobalVariableDefs.obj (EmuBModeVar)
FlashCallbackVar
* 1 00000d02 00000002 UNINITIALIZED
00000d02 00000002 DSP2803x_GlobalVariableDefs.obj (FlashCallbackVar)
FlashScalingVar
* 1 00000d04 00000002 UNINITIALIZED
00000d04 00000002 DSP2803x_GlobalVariableDefs.obj (FlashScalingVar)
Cla1RegsFile
* 1 00001400 00000040 UNINITIALIZED
00001400 00000040 DSP2803x_GlobalVariableDefs.obj (Cla1RegsFile)
Cla1ToCpuMsgRAM
* 1 00001480 00000012 UNINITIALIZED
00001480 00000012 cla.obj (Cla1ToCpuMsgRAM)
CpuToCla1MsgRAM
* 1 00001500 00000004 UNINITIALIZED
00001500 00000004 cla.obj (CpuToCla1MsgRAM)
ECanaRegsFile
* 1 00006000 00000034 UNINITIALIZED
00006000 00000034 DSP2803x_GlobalVariableDefs.obj (ECanaRegsFile)
ECanaLAMRegsFile
* 1 00006040 00000040 UNINITIALIZED
00006040 00000040 DSP2803x_GlobalVariableDefs.obj (ECanaLAMRegsFile)
ECanaMOTSRegsFile
* 1 00006080 00000040 UNINITIALIZED
00006080 00000040 DSP2803x_GlobalVariableDefs.obj (ECanaMOTSRegsFile)
ECanaMOTORegsFile
* 1 000060c0 00000040 UNINITIALIZED
000060c0 00000040 DSP2803x_GlobalVariableDefs.obj (ECanaMOTORegsFile)
ECanaMboxesFile
* 1 00006100 00000100 UNINITIALIZED
00006100 00000100 DSP2803x_GlobalVariableDefs.obj (ECanaMboxesFile)
Comp1RegsFile
* 1 00006400 00000014 UNINITIALIZED
00006400 00000014 DSP2803x_GlobalVariableDefs.obj (Comp1RegsFile)
Comp2RegsFile
* 1 00006420 00000014 UNINITIALIZED
00006420 00000014 DSP2803x_GlobalVariableDefs.obj (Comp2RegsFile)
Comp3RegsFile
* 1 00006440 00000014 UNINITIALIZED
00006440 00000014 DSP2803x_GlobalVariableDefs.obj (Comp3RegsFile)
EPwm1RegsFile
* 1 00006800 00000040 UNINITIALIZED
00006800 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm1RegsFile)
EPwm2RegsFile
* 1 00006840 00000040 UNINITIALIZED
00006840 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm2RegsFile)
EPwm3RegsFile
* 1 00006880 00000040 UNINITIALIZED
00006880 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm3RegsFile)
EPwm4RegsFile
* 1 000068c0 00000040 UNINITIALIZED
000068c0 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm4RegsFile)
EPwm5RegsFile
* 1 00006900 00000040 UNINITIALIZED
00006900 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm5RegsFile)
EPwm6RegsFile
* 1 00006940 00000040 UNINITIALIZED
00006940 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm6RegsFile)
EPwm7RegsFile
* 1 00006980 00000040 UNINITIALIZED
00006980 00000040 DSP2803x_GlobalVariableDefs.obj (EPwm7RegsFile)
ECap1RegsFile
* 1 00006a00 00000020 UNINITIALIZED
00006a00 00000020 DSP2803x_GlobalVariableDefs.obj (ECap1RegsFile)
HRCap1RegsFile
* 1 00006ac0 00000020 UNINITIALIZED
00006ac0 00000020 DSP2803x_GlobalVariableDefs.obj (HRCap1RegsFile)
HRCap2RegsFile
* 1 00006ae0 00000020 UNINITIALIZED
00006ae0 00000020 DSP2803x_GlobalVariableDefs.obj (HRCap2RegsFile)
EQep1RegsFile
* 1 00006b00 00000040 UNINITIALIZED
00006b00 00000040 DSP2803x_GlobalVariableDefs.obj (EQep1RegsFile)
LinaRegsFile
* 1 00006c00 0000004a UNINITIALIZED
00006c00 0000004a DSP2803x_GlobalVariableDefs.obj (LinaRegsFile)
GpioCtrlRegsFile
* 1 00006f80 00000040 UNINITIALIZED
00006f80 00000040 DSP2803x_GlobalVariableDefs.obj (GpioCtrlRegsFile)
GpioDataRegsFile
* 1 00006fc0 00000020 UNINITIALIZED
00006fc0 00000020 DSP2803x_GlobalVariableDefs.obj (GpioDataRegsFile)
GpioIntRegsFile
* 1 00006fe0 0000000c UNINITIALIZED
00006fe0 0000000c DSP2803x_GlobalVariableDefs.obj (GpioIntRegsFile)
SysCtrlRegsFile
* 1 00007010 00000020 UNINITIALIZED
00007010 00000020 DSP2803x_GlobalVariableDefs.obj (SysCtrlRegsFile)
SpiaRegsFile
* 1 00007040 00000010 UNINITIALIZED
00007040 00000010 DSP2803x_GlobalVariableDefs.obj (SpiaRegsFile)
SciaRegsFile
* 1 00007050 00000010 UNINITIALIZED
00007050 00000010 DSP2803x_GlobalVariableDefs.obj (SciaRegsFile)
NmiIntruptRegsFile
* 1 00007060 00000010 UNINITIALIZED
00007060 00000010 DSP2803x_GlobalVariableDefs.obj (NmiIntruptRegsFile)
XIntruptRegsFile
* 1 00007070 00000010 UNINITIALIZED
00007070 00000010 DSP2803x_GlobalVariableDefs.obj (XIntruptRegsFile)
AdcRegsFile
* 1 00007100 00000050 UNINITIALIZED
00007100 00000050 DSP2803x_GlobalVariableDefs.obj (AdcRegsFile)
SpibRegsFile
* 1 00007740 00000010 UNINITIALIZED
00007740 00000010 DSP2803x_GlobalVariableDefs.obj (SpibRegsFile)
I2caRegsFile
* 1 00007900 00000022 UNINITIALIZED
00007900 00000022 DSP2803x_GlobalVariableDefs.obj (I2caRegsFile)
.ebss 1 00008000 00000244 UNINITIALIZED
00008000 000001ce modbus.obj (.ebss)
000081ce 00000018 DSP2803x_CpuTimers.obj (.ebss)
000081e6 0000000c pwm_run_stop.obj (.ebss)
000081f2 00000004 epwm.obj (.ebss)
000081f6 00000004 rts2800_ml.lib : _lock.obj (.ebss)
000081fa 00000004 : exit.obj (.ebss)
000081fe 00000002 main.obj (.ebss)
00008200 00000042 protec_state.obj (.ebss)
00008242 00000002 timer.obj (.ebss)
Cla1DataRam0
* 1 00008800 00000340 UNINITIALIZED
00008800 00000340 cla.obj (Cla1DataRam0)
CLAscratch
* 1 00008d68 00000104 UNINITIALIZED
00008d68 00000002 CLAlog10.obj (CLAscratch)
00008d6a 00000100 --HOLE--
00008e6a 00000002 CLAmath.lib : CLAsqrt.obj (CLAscratch)
PartIdRegsFile
* 1 003d7e80 00000001 UNINITIALIZED
003d7e80 00000001 DSP2803x_GlobalVariableDefs.obj (PartIdRegsFile)
CLA1mathTables
* 1 003f4000 00000228 RUN ADDR = 00008b40
003f4000 00000156 CLAmath.lib : CLASinCosTable.obj (CLA1mathTables)
003f4156 000000d2 : CLAlnTable.obj (CLA1mathTables)
.const_cla
* 1 003f4228 00000000 UNINITIALIZEDRUN ADDR = 00008d68
CsmPwlFile
* 1 003f7ff8 00000008 UNINITIALIZED
003f7ff8 00000008 DSP2803x_GlobalVariableDefs.obj (CsmPwlFile)

GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
address name
-------- ----
003f2000 .text
003f34d0 C$$EXIT
00000100 CLA_SCRATCHPAD_SIZE
003f2e74 FD$$MPY
003f3429 FD$$TOL
003f2ffa FS$$ADD
003f3519 FS$$CMP
003f2ef7 FS$$DIV
003f30e0 FS$$MPY
003f2ff5 FS$$SUB
003f3481 FS$$TOFD
003f337e FS$$TOI
003f3306 FS$$TOL
003f33e7 FS$$TOUL
003f3448 I$$TOFD
003f349d L$$TOFS
003f3557 UL$$TOFS
003f2bae _ADCINT1_ISR
003f2ba9 _ADCINT2_ISR
003f2ba4 _ADCINT3_ISR
003f2b9f _ADCINT4_ISR
003f2b9a _ADCINT5_ISR
003f2b95 _ADCINT6_ISR
003f2b90 _ADCINT7_ISR
003f2b8b _ADCINT8_ISR
003f2b86 _ADCINT9_ISR
003f28d2 _AdcChanSelect
003f292a _AdcConversion
003f2a12 _AdcOffsetSelfCal
00007100 _AdcRegs
00000b00 _AdcResult
00009348 _AdcSample
00009462 _AverageCalc
003f2b81 _CLA1_INT1_ISR
003f2b7c _CLA1_INT2_ISR
003f2b77 _CLA1_INT3_ISR
003f2b72 _CLA1_INT4_ISR
003f2b6d _CLA1_INT5_ISR
003f2b68 _CLA1_INT6_ISR
003f2b63 _CLA1_INT7_ISR
003f2b5e _CLA1_INT8_ISR
00008c9c _CLABIAS
00008c9a _CLALNV10
00008c96 _CLALNV2
00008c98 _CLALNVe
00008c9e _CLALN_TABLE_MASK1
00008ca0 _CLALN_TABLE_MASK2
00008ca2 _CLALnTable
00008d68 _CLALnTableEnd
000095a2 _CLAcos
00008b80 _CLAcosTable
00008c82 _CLAcosTableEnd
000095dc _CLAln
00009562 _CLAlog10
00009616 _CLAsin
00008b40 _CLAsinTable
00008c40 _CLAsinTableEnd
00008b40 _CLAsincosTable
00008c96 _CLAsincosTableEnd
00008c8a _CLAsincosTable_Coef0
00008c8c _CLAsincosTable_Coef1
00008c8e _CLAsincosTable_Coef1_pos
00008c90 _CLAsincosTable_Coef2
00008c92 _CLAsincosTable_Coef3
00008c94 _CLAsincosTable_Coef3_neg
00008b80 _CLAsincosTable_Cos0
00008b40 _CLAsincosTable_Sin0
00008c88 _CLAsincosTable_TABLE_MASK
00008c82 _CLAsincosTable_TABLE_SIZE
00008c84 _CLAsincosTable_TABLE_SIZEDivTwoPi
00008c86 _CLAsincosTable_TwoPiDivTABLE_SIZE
00009650 _CLAsqrt
003f3502 _CRC16
00009000 _Cla1Prog_Start
00001400 _Cla1Regs
00009000 _Cla1Task8
003ee670 _Cla1funcsLoadEnd
00000670 _Cla1funcsLoadSize
003ee000 _Cla1funcsLoadStart
00009000 _Cla1funcsRunStart
003f4228 _Cla1mathTablesLoadEnd
00000228 _Cla1mathTablesLoadSize
003f4000 _Cla1mathTablesLoadStart
00008b40 _Cla1mathTablesRunStart
00006400 _Comp1Regs
00006420 _Comp2Regs
00006440 _Comp3Regs
003f2de5 _ConfigAdc
003f313a _ConfigCla
003f32b4 _ConfigCpuTimer
003f31b4 _ConfigEcap
003f285c _ConfigEpwm
003f33a3 _Config_CPUTimer
000081de _CpuTimer0
00000c00 _CpuTimer0Regs
000081ce _CpuTimer1
00000c08 _CpuTimer1Regs
000081d6 _CpuTimer2
00000c10 _CpuTimer2Regs
003f7ff8 _CsmPwl
00000ae0 _CsmRegs
003f2ccb _CsmUnlock
003f2b59 _DATALOG_ISR
003f35a1 _DSP28x_DisableInt
003f35a5 _DSP28x_RestoreInt
0000006d _DSP28x_usDelay
00000880 _DevEmuRegs
003f2bf5 _DisableDog
003f2b54 _ECAN0INTA_ISR
003f2b4f _ECAN1INTA_ISR
003f2b4a _ECAP1_INT_ISR
00006040 _ECanaLAMRegs
000060c0 _ECanaMOTORegs
00006080 _ECanaMOTSRegs
00006100 _ECanaMboxes
00006000 _ECanaRegs
00006a00 _ECap1Regs
003f2b45 _EMPTY_ISR
003f2b40 _EMUINT_ISR
003f2b3b _EPWM1_INT_ISR
003f2b36 _EPWM1_TZINT_ISR
003f2b31 _EPWM2_INT_ISR
003f2b2c _EPWM2_TZINT_ISR
003f2b27 _EPWM3_INT_ISR
003f2b22 _EPWM3_TZINT_ISR
003f2b1d _EPWM4_INT_ISR
003f2b18 _EPWM4_TZINT_ISR
003f2b13 _EPWM5_INT_ISR
003f2b0e _EPWM5_TZINT_ISR
003f2b09 _EPWM6_INT_ISR
003f2b04 _EPWM6_TZINT_ISR
003f2aff _EPWM7_INT_ISR
003f2afa _EPWM7_TZINT_ISR
00006800 _EPwm1Regs
00006840 _EPwm2Regs
00006880 _EPwm3Regs
000068c0 _EPwm4Regs
00006900 _EPwm5Regs
00006940 _EPwm6Regs
00006980 _EPwm7Regs
003f2af5 _EQEP1_INT_ISR
00006b00 _EQep1Regs
00000d01 _EmuBMode
00000d00 _EmuKey
003f334e _EnableInterrupts
003f2bfd _ExtOscSel
00000a80 _FlashRegs
00000d04 _Flash_CPUScaleFactor
00000d02 _Flash_CallbackPtr
003f26b8 _GpiO_state
00006f80 _GpioCtrlRegs
00006fc0 _GpioDataRegs
00006fe0 _GpioIntRegs
00009300 _Grid_postive_negetive
003f2af0 _HRCAP1_INT_ISR
003f2aeb _HRCAP2_INT_ISR
00006ac0 _HRCap1Regs
00006ae0 _HRCap2Regs
003f2ae6 _I2CINT1A_ISR
003f2ae1 _I2CINT2A_ISR
00007900 _I2caRegs
003f2adc _ILLEGAL_ISR
003f2ad7 _INT13_ISR
003f2ad2 _INT14_ISR
003fead8 _IQ10mpyRndSatTable
003feacc _IQ11mpyRndSatTable
003feac0 _IQ12mpyRndSatTable
003feab4 _IQ13mpyRndSatTable
003feaa8 _IQ14mpyRndSatTable
003fea9c _IQ15mpyRndSatTable
003fea90 _IQ16mpyRndSatTable
003fea84 _IQ17mpyRndSatTable
003fea78 _IQ18mpyRndSatTable
003fea6c _IQ19mpyRndSatTable
003feb44 _IQ1mpyRndSatTable
003fea60 _IQ20mpyRndSatTable
003fea54 _IQ21mpyRndSatTable
003fea48 _IQ22mpyRndSatTable
003fea3c _IQ23mpyRndSatTable
003fea30 _IQ24mpyRndSatTable
003fea24 _IQ25mpyRndSatTable
003fea18 _IQ26mpyRndSatTable
003fea0c _IQ27mpyRndSatTable
003fea00 _IQ28mpyRndSatTable
003fe9f4 _IQ29mpyRndSatTable
003feb38 _IQ2mpyRndSatTable
003fe9e8 _IQ30mpyRndSatTable
003feb2c _IQ3mpyRndSatTable
003feb20 _IQ4mpyRndSatTable
003feb14 _IQ5mpyRndSatTable
003feb08 _IQ6mpyRndSatTable
003feafc _IQ7mpyRndSatTable
003feaf0 _IQ8mpyRndSatTable
003feae4 _IQ9mpyRndSatTable
003fe824 _IQatan2HalfPITable
003fe862 _IQatan2Table
003fe9e8 _IQatan2TableEnd
003fe100 _IQcosTable
003fe502 _IQcosTableEnd
003fe502 _IQdivRoundSatTable
003fe510 _IQdivTable
003fe712 _IQdivTableEnd
003fe712 _IQisqrtRoundSatTable
003fe722 _IQisqrtTable
003fe824 _IQisqrtTableEnd
003fe9e8 _IQmpyRndSatTable
003feb50 _IQmpyRndSatTableEnd
003fe000 _IQsinTable
003fe400 _IQsinTableEnd
003fe712 _IQsqrtRoundSatTable
003fe722 _IQsqrtTable
003fe824 _IQsqrtTableEnd
0000148c _Ia
00008236 _Ia_OVER_ALARM
0000148e _Ib
00008238 _Ib_OVER_ALARM
00001484 _Ic
00008240 _Ic_OVER_ALARM
003f28b4 _InitAdc
003f288e _InitAdcAio
003f329f _InitCpuTimers
003f2f95 _InitECan
003f2f7a _InitECanGpio
003f2f95 _InitECana
003f2f7a _InitECanaGpio
003f3543 _InitECap
003f3530 _InitECap1Gpio
003f3530 _InitECapGpio
003f3185 _InitECapture
003f2de4 _InitEPwm
003f281a _InitEPwm1Example
003f2d36 _InitEPwm1Gpio
003f27da _InitEPwm2Example
003f2d4c _InitEPwm2Gpio
003f279a _InitEPwm3Example
003f2d62 _InitEPwm3Gpio
003f2755 _InitEPwm4Example
003f2d7a _InitEPwm4Gpio
003f2710 _InitEPwm5Example
003f2d92 _InitEPwm5Gpio
003f26cb _InitEPwm6Example
003f2da8 _InitEPwm6Gpio
003f2dbe _InitEPwm7Gpio
003f2dd5 _InitEPwmGpio
003f2d1e _InitEPwmSyncGpio
00000050 _InitFlash
003f3544 _InitGpio
003f23c5 _InitModbus
003f306d _InitMyGpio
003f2c63 _InitPeripheralClocks
003f332f _InitPieCtrl
003f356a _InitPieVectTable
003f2c15 _InitPll
003f3480 _InitSci
003f3465 _InitSciGpio
003f320a _InitScia
003f3465 _InitSciaGpio
003f2ca8 _InitSysCtrl
003f2cf9 _InitTzGpio
003f2be5 _IntOsc1Sel
003f2bd1 _IntOsc2Sel
003f2acd _LIN0INTA_ISR
003f2ac8 _LIN1INTA_ISR
003f2ac3 _LUF_ISR
003f2abe _LVF_ISR
00006c00 _LinaRegs
003f215a _ModbusCommunication
000080c0 _ModbusModule
00008040 _ModbusRxTxValue
003f2079 _ModbusSlaveReadRegAnswer
00008002 _ModbusSlaveReadRegAnswerFlg
003f2049 _ModbusSlaveSetNRegAnswer
00008003 _ModbusSlaveSetNRegAnswerFlg
003f2ab9 _NMI_ISR
00007060 _NmiIntruptRegs
00001488 _PCBTemperature
003f2ab4 _PIE_RESERVED
003d7e80 _PartIdRegs
00001502 _Period
00000ce0 _PieCtrlRegs
00000d00 _PieVectTable
003f6000 _PieVectTableInit
003f23d7 _Protect
003f2aaf _RTOSINT_ISR
003f20ca _RTUSlaveFrameAnalyse
00000021 _RamfuncsLoadSize
003f0000 _RamfuncsLoadStart
00000050 _RamfuncsRunStart
003f201b _ReadSci
00001500 _RunEnableFlag
0000820c _Run_flag_able
003f2aaa _SCIRXINTA_ISR
003f2aa5 _SCITXINTA_ISR
003f2aa0 _SPIRXINTA_ISR
003f2a9b _SPIRXINTB_ISR
003f2a96 _SPITXINTA_ISR
003f2a91 _SPITXINTB_ISR
00007050 _SciaRegs
003f2bc7 _ServiceDog
00007040 _SpiaRegs
00007740 _SpibRegs
00008004 _StartMode
00008001 _StopMode
00008207 _Stop_flag_able
00007010 _SysCtrlRegs
00000985 _SysPwrCtrlRegs
0000823a _TEMPUTURE_ALARM
003f2a8c _TINT0_ISR
003f2a87 _USER10_ISR
003f2a82 _USER11_ISR
003f2a7d _USER12_ISR
003f2a78 _USER1_ISR
003f2a73 _USER2_ISR
003f2a6e _USER3_ISR
003f2a69 _USER4_ISR
003f2a64 _USER5_ISR
003f2a5f _USER6_ISR
003f2a5a _USER7_ISR
003f2a55 _USER8_ISR
003f2a50 _USER9_ISR
00001486 _Uab
00008220 _Uab_OVER_ALARM
00008224 _Uab_UNDER_ALARM
0000148a _Ubc
00008222 _Ubc_OVER_ALARM
00008226 _Ubc_UNDER_ALARM
00001490 _Uca
00008228 _Uca_OVER_ALARM
0000823e _Uca_UNDER_ALARM
00008806 _Ud
00008802 _Udfil
00008808 _Uq
00008804 _Uqfil
003f2a4b _WAKEINT_ISR
003f2000 _WriteSci
003f2a46 _XINT1_ISR
003f2a41 _XINT2_ISR
003f2a3c _XINT3_ISR
00007070 _XIntruptRegs
003f2bb3 _XtalOscSel
003f653a __IQ10div
003f6581 __IQ10toF
00000600 __STACK_END
00000200 __STACK_SIZE
00000001 __TI_args_main
ffffffff ___binit__
ffffffff ___c_args__
003f6304 ___cinit__
003f35a8 ___etext__
003f3408 ___memcpy_ff
ffffffff ___pinit__
003f2000 ___text__
003f34b7 __args_main
00008e6a __cla_scratchpad_end
00008d68 __cla_scratchpad_start
000081fa __cleanup_ptr
000081fc __dtors_ptr
000081f8 __lock
003f3598 __nop
003f3594 __register_lock
003f3590 __register_unlock
00000400 __stack
000081f6 __unlock
003f34d0 _abort
00008840 _ad
000081ec _angl1
000081ea _angl2
000081f0 _angl3
003f6100 _auchCRCHi
003f6200 _auchCRCLo
003f325b _c_int00
003f3587 _cla1_task8_isr
00008801 _cnt
000081e7 _cnt1
000081e6 _cnt2
000081e9 _cnt3
000081f3 _cnt_en_run
003f33c6 _cpu_timer0_isr
003f32da _ecap1_isr
003f357b _epilog_c28x_1
003f357f _epilog_c28x_2
003f3371 _epwm4_isr
003f3364 _epwm5_isr
003f3357 _epwm6_isr
003f34d2 _exit
00001482 _grid_alpha
00008800 _index
00008006 _index_modbus
00008242 _index_time2
000081f4 _led_fault_cnt
000081f2 _led_run_cnt
00001481 _lock_flag
003f3216 _main
00001480 _postive_negetive_flag
003f34e9 _prolog_c28x_1
003f34ed _prolog_c28x_2
003f34f5 _prolog_c28x_3
003f2a37 _rsvd_ISR
003f3202 _scia_fifo_init
003f31cf _scia_init
0000880a _state
000081e8 _stateword
000081fe _testcntcnt
000081ee _timepwm
ffffffff binit
003f6304 cinit
003f7ff6 code_start
003f35a8 etext
ffffffff pinit

GLOBAL SYMBOLS: SORTED BY Symbol Address
address name
-------- ----
00000001 __TI_args_main
00000021 _RamfuncsLoadSize
00000050 _InitFlash
00000050 _RamfuncsRunStart
0000006d _DSP28x_usDelay
00000100 CLA_SCRATCHPAD_SIZE
00000200 __STACK_SIZE
00000228 _Cla1mathTablesLoadSize
00000400 __stack
00000600 __STACK_END
00000670 _Cla1funcsLoadSize
00000880 _DevEmuRegs
00000985 _SysPwrCtrlRegs
00000a80 _FlashRegs
00000ae0 _CsmRegs
00000b00 _AdcResult
00000c00 _CpuTimer0Regs
00000c08 _CpuTimer1Regs
00000c10 _CpuTimer2Regs
00000ce0 _PieCtrlRegs
00000d00 _EmuKey
00000d00 _PieVectTable
00000d01 _EmuBMode
00000d02 _Flash_CallbackPtr
00000d04 _Flash_CPUScaleFactor
00001400 _Cla1Regs
00001480 _postive_negetive_flag
00001481 _lock_flag
00001482 _grid_alpha
00001484 _Ic
00001486 _Uab
00001488 _PCBTemperature
0000148a _Ubc
0000148c _Ia
0000148e _Ib
00001490 _Uca
00001500 _RunEnableFlag
00001502 _Period
00006000 _ECanaRegs
00006040 _ECanaLAMRegs
00006080 _ECanaMOTSRegs
000060c0 _ECanaMOTORegs
00006100 _ECanaMboxes
00006400 _Comp1Regs
00006420 _Comp2Regs
00006440 _Comp3Regs
00006800 _EPwm1Regs
00006840 _EPwm2Regs
00006880 _EPwm3Regs
000068c0 _EPwm4Regs
00006900 _EPwm5Regs
00006940 _EPwm6Regs
00006980 _EPwm7Regs
00006a00 _ECap1Regs
00006ac0 _HRCap1Regs
00006ae0 _HRCap2Regs
00006b00 _EQep1Regs
00006c00 _LinaRegs
00006f80 _GpioCtrlRegs
00006fc0 _GpioDataRegs
00006fe0 _GpioIntRegs
00007010 _SysCtrlRegs
00007040 _SpiaRegs
00007050 _SciaRegs
00007060 _NmiIntruptRegs
00007070 _XIntruptRegs
00007100 _AdcRegs
00007740 _SpibRegs
00007900 _I2caRegs
00008001 _StopMode
00008002 _ModbusSlaveReadRegAnswerFlg
00008003 _ModbusSlaveSetNRegAnswerFlg
00008004 _StartMode
00008006 _index_modbus
00008040 _ModbusRxTxValue
000080c0 _ModbusModule
000081ce _CpuTimer1
000081d6 _CpuTimer2
000081de _CpuTimer0
000081e6 _cnt2
000081e7 _cnt1
000081e8 _stateword
000081e9 _cnt3
000081ea _angl2
000081ec _angl1
000081ee _timepwm
000081f0 _angl3
000081f2 _led_run_cnt
000081f3 _cnt_en_run
000081f4 _led_fault_cnt
000081f6 __unlock
000081f8 __lock
000081fa __cleanup_ptr
000081fc __dtors_ptr
000081fe _testcntcnt
00008207 _Stop_flag_able
0000820c _Run_flag_able
00008220 _Uab_OVER_ALARM
00008222 _Ubc_OVER_ALARM
00008224 _Uab_UNDER_ALARM
00008226 _Ubc_UNDER_ALARM
00008228 _Uca_OVER_ALARM
00008236 _Ia_OVER_ALARM
00008238 _Ib_OVER_ALARM
0000823a _TEMPUTURE_ALARM
0000823e _Uca_UNDER_ALARM
00008240 _Ic_OVER_ALARM
00008242 _index_time2
00008800 _index
00008801 _cnt
00008802 _Udfil
00008804 _Uqfil
00008806 _Ud
00008808 _Uq
0000880a _state
00008840 _ad
00008b40 _CLAsinTable
00008b40 _CLAsincosTable
00008b40 _CLAsincosTable_Sin0
00008b40 _Cla1mathTablesRunStart
00008b80 _CLAcosTable
00008b80 _CLAsincosTable_Cos0
00008c40 _CLAsinTableEnd
00008c82 _CLAcosTableEnd
00008c82 _CLAsincosTable_TABLE_SIZE
00008c84 _CLAsincosTable_TABLE_SIZEDivTwoPi
00008c86 _CLAsincosTable_TwoPiDivTABLE_SIZE
00008c88 _CLAsincosTable_TABLE_MASK
00008c8a _CLAsincosTable_Coef0
00008c8c _CLAsincosTable_Coef1
00008c8e _CLAsincosTable_Coef1_pos
00008c90 _CLAsincosTable_Coef2
00008c92 _CLAsincosTable_Coef3
00008c94 _CLAsincosTable_Coef3_neg
00008c96 _CLALNV2
00008c96 _CLAsincosTableEnd
00008c98 _CLALNVe
00008c9a _CLALNV10
00008c9c _CLABIAS
00008c9e _CLALN_TABLE_MASK1
00008ca0 _CLALN_TABLE_MASK2
00008ca2 _CLALnTable
00008d68 _CLALnTableEnd
00008d68 __cla_scratchpad_start
00008e6a __cla_scratchpad_end
00009000 _Cla1Prog_Start
00009000 _Cla1Task8
00009000 _Cla1funcsRunStart
00009300 _Grid_postive_negetive
00009348 _AdcSample
00009462 _AverageCalc
00009562 _CLAlog10
000095a2 _CLAcos
000095dc _CLAln
00009616 _CLAsin
00009650 _CLAsqrt
003d7e80 _PartIdRegs
003ee000 _Cla1funcsLoadStart
003ee670 _Cla1funcsLoadEnd
003f0000 _RamfuncsLoadStart
003f2000 .text
003f2000 _WriteSci
003f2000 ___text__
003f201b _ReadSci
003f2049 _ModbusSlaveSetNRegAnswer
003f2079 _ModbusSlaveReadRegAnswer
003f20ca _RTUSlaveFrameAnalyse
003f215a _ModbusCommunication
003f23c5 _InitModbus
003f23d7 _Protect
003f26b8 _GpiO_state
003f26cb _InitEPwm6Example
003f2710 _InitEPwm5Example
003f2755 _InitEPwm4Example
003f279a _InitEPwm3Example
003f27da _InitEPwm2Example
003f281a _InitEPwm1Example
003f285c _ConfigEpwm
003f288e _InitAdcAio
003f28b4 _InitAdc
003f28d2 _AdcChanSelect
003f292a _AdcConversion
003f2a12 _AdcOffsetSelfCal
003f2a37 _rsvd_ISR
003f2a3c _XINT3_ISR
003f2a41 _XINT2_ISR
003f2a46 _XINT1_ISR
003f2a4b _WAKEINT_ISR
003f2a50 _USER9_ISR
003f2a55 _USER8_ISR
003f2a5a _USER7_ISR
003f2a5f _USER6_ISR
003f2a64 _USER5_ISR
003f2a69 _USER4_ISR
003f2a6e _USER3_ISR
003f2a73 _USER2_ISR
003f2a78 _USER1_ISR
003f2a7d _USER12_ISR
003f2a82 _USER11_ISR
003f2a87 _USER10_ISR
003f2a8c _TINT0_ISR
003f2a91 _SPITXINTB_ISR
003f2a96 _SPITXINTA_ISR
003f2a9b _SPIRXINTB_ISR
003f2aa0 _SPIRXINTA_ISR
003f2aa5 _SCITXINTA_ISR
003f2aaa _SCIRXINTA_ISR
003f2aaf _RTOSINT_ISR
003f2ab4 _PIE_RESERVED
003f2ab9 _NMI_ISR
003f2abe _LVF_ISR
003f2ac3 _LUF_ISR
003f2ac8 _LIN1INTA_ISR
003f2acd _LIN0INTA_ISR
003f2ad2 _INT14_ISR
003f2ad7 _INT13_ISR
003f2adc _ILLEGAL_ISR
003f2ae1 _I2CINT2A_ISR
003f2ae6 _I2CINT1A_ISR
003f2aeb _HRCAP2_INT_ISR
003f2af0 _HRCAP1_INT_ISR
003f2af5 _EQEP1_INT_ISR
003f2afa _EPWM7_TZINT_ISR
003f2aff _EPWM7_INT_ISR
003f2b04 _EPWM6_TZINT_ISR
003f2b09 _EPWM6_INT_ISR
003f2b0e _EPWM5_TZINT_ISR
003f2b13 _EPWM5_INT_ISR
003f2b18 _EPWM4_TZINT_ISR
003f2b1d _EPWM4_INT_ISR
003f2b22 _EPWM3_TZINT_ISR
003f2b27 _EPWM3_INT_ISR
003f2b2c _EPWM2_TZINT_ISR
003f2b31 _EPWM2_INT_ISR
003f2b36 _EPWM1_TZINT_ISR
003f2b3b _EPWM1_INT_ISR
003f2b40 _EMUINT_ISR
003f2b45 _EMPTY_ISR
003f2b4a _ECAP1_INT_ISR
003f2b4f _ECAN1INTA_ISR
003f2b54 _ECAN0INTA_ISR
003f2b59 _DATALOG_ISR
003f2b5e _CLA1_INT8_ISR
003f2b63 _CLA1_INT7_ISR
003f2b68 _CLA1_INT6_ISR
003f2b6d _CLA1_INT5_ISR
003f2b72 _CLA1_INT4_ISR
003f2b77 _CLA1_INT3_ISR
003f2b7c _CLA1_INT2_ISR
003f2b81 _CLA1_INT1_ISR
003f2b86 _ADCINT9_ISR
003f2b8b _ADCINT8_ISR
003f2b90 _ADCINT7_ISR
003f2b95 _ADCINT6_ISR
003f2b9a _ADCINT5_ISR
003f2b9f _ADCINT4_ISR
003f2ba4 _ADCINT3_ISR
003f2ba9 _ADCINT2_ISR
003f2bae _ADCINT1_ISR
003f2bb3 _XtalOscSel
003f2bc7 _ServiceDog
003f2bd1 _IntOsc2Sel
003f2be5 _IntOsc1Sel
003f2bf5 _DisableDog
003f2bfd _ExtOscSel
003f2c15 _InitPll
003f2c63 _InitPeripheralClocks
003f2ca8 _InitSysCtrl
003f2ccb _CsmUnlock
003f2cf9 _InitTzGpio
003f2d1e _InitEPwmSyncGpio
003f2d36 _InitEPwm1Gpio
003f2d4c _InitEPwm2Gpio
003f2d62 _InitEPwm3Gpio
003f2d7a _InitEPwm4Gpio
003f2d92 _InitEPwm5Gpio
003f2da8 _InitEPwm6Gpio
003f2dbe _InitEPwm7Gpio
003f2dd5 _InitEPwmGpio
003f2de4 _InitEPwm
003f2de5 _ConfigAdc
003f2e74 FD$$MPY
003f2ef7 FS$$DIV
003f2f7a _InitECanGpio
003f2f7a _InitECanaGpio
003f2f95 _InitECan
003f2f95 _InitECana
003f2ff5 FS$$SUB
003f2ffa FS$$ADD
003f306d _InitMyGpio
003f30e0 FS$$MPY
003f313a _ConfigCla
003f3185 _InitECapture
003f31b4 _ConfigEcap
003f31cf _scia_init
003f3202 _scia_fifo_init
003f320a _InitScia
003f3216 _main
003f325b _c_int00
003f329f _InitCpuTimers
003f32b4 _ConfigCpuTimer
003f32da _ecap1_isr
003f3306 FS$$TOL
003f332f _InitPieCtrl
003f334e _EnableInterrupts
003f3357 _epwm6_isr
003f3364 _epwm5_isr
003f3371 _epwm4_isr
003f337e FS$$TOI
003f33a3 _Config_CPUTimer
003f33c6 _cpu_timer0_isr
003f33e7 FS$$TOUL
003f3408 ___memcpy_ff
003f3429 FD$$TOL
003f3448 I$$TOFD
003f3465 _InitSciGpio
003f3465 _InitSciaGpio
003f3480 _InitSci
003f3481 FS$$TOFD
003f349d L$$TOFS
003f34b7 __args_main
003f34d0 C$$EXIT
003f34d0 _abort
003f34d2 _exit
003f34e9 _prolog_c28x_1
003f34ed _prolog_c28x_2
003f34f5 _prolog_c28x_3
003f3502 _CRC16
003f3519 FS$$CMP
003f3530 _InitECap1Gpio
003f3530 _InitECapGpio
003f3543 _InitECap
003f3544 _InitGpio
003f3557 UL$$TOFS
003f356a _InitPieVectTable
003f357b _epilog_c28x_1
003f357f _epilog_c28x_2
003f3587 _cla1_task8_isr
003f3590 __register_unlock
003f3594 __register_lock
003f3598 __nop
003f35a1 _DSP28x_DisableInt
003f35a5 _DSP28x_RestoreInt
003f35a8 ___etext__
003f35a8 etext
003f4000 _Cla1mathTablesLoadStart
003f4228 _Cla1mathTablesLoadEnd
003f6000 _PieVectTableInit
003f6100 _auchCRCHi
003f6200 _auchCRCLo
003f6304 ___cinit__
003f6304 cinit
003f653a __IQ10div
003f6581 __IQ10toF
003f7ff6 code_start
003f7ff8 _CsmPwl
003fe000 _IQsinTable
003fe100 _IQcosTable
003fe400 _IQsinTableEnd
003fe502 _IQcosTableEnd
003fe502 _IQdivRoundSatTable
003fe510 _IQdivTable
003fe712 _IQdivTableEnd
003fe712 _IQisqrtRoundSatTable
003fe712 _IQsqrtRoundSatTable
003fe722 _IQisqrtTable
003fe722 _IQsqrtTable
003fe824 _IQatan2HalfPITable
003fe824 _IQisqrtTableEnd
003fe824 _IQsqrtTableEnd
003fe862 _IQatan2Table
003fe9e8 _IQ30mpyRndSatTable
003fe9e8 _IQatan2TableEnd
003fe9e8 _IQmpyRndSatTable
003fe9f4 _IQ29mpyRndSatTable
003fea00 _IQ28mpyRndSatTable
003fea0c _IQ27mpyRndSatTable
003fea18 _IQ26mpyRndSatTable
003fea24 _IQ25mpyRndSatTable
003fea30 _IQ24mpyRndSatTable
003fea3c _IQ23mpyRndSatTable
003fea48 _IQ22mpyRndSatTable
003fea54 _IQ21mpyRndSatTable
003fea60 _IQ20mpyRndSatTable
003fea6c _IQ19mpyRndSatTable
003fea78 _IQ18mpyRndSatTable
003fea84 _IQ17mpyRndSatTable
003fea90 _IQ16mpyRndSatTable
003fea9c _IQ15mpyRndSatTable
003feaa8 _IQ14mpyRndSatTable
003feab4 _IQ13mpyRndSatTable
003feac0 _IQ12mpyRndSatTable
003feacc _IQ11mpyRndSatTable
003fead8 _IQ10mpyRndSatTable
003feae4 _IQ9mpyRndSatTable
003feaf0 _IQ8mpyRndSatTable
003feafc _IQ7mpyRndSatTable
003feb08 _IQ6mpyRndSatTable
003feb14 _IQ5mpyRndSatTable
003feb20 _IQ4mpyRndSatTable
003feb2c _IQ3mpyRndSatTable
003feb38 _IQ2mpyRndSatTable
003feb44 _IQ1mpyRndSatTable
003feb50 _IQmpyRndSatTableEnd
ffffffff ___binit__
ffffffff ___c_args__
ffffffff ___pinit__
ffffffff binit
ffffffff pinit
[409 symbols]

下次提供这类信息的时候，请不要简单地粘贴代码在回帖里，可以使用添加附件的形式。
你需要我们高效地帮你解决问题，也请考虑一下如何会比较方便我们查看和对比。
.
你的问题应该在于内存分配的页处理上，对于变量和数组来说，编译器会以页(data page)进行分配，你可以查看指令集手册spru430搜索该关键字了解。
简单来说，它是以64个words为单位进行分配，因此地址是按照尾数0x40的倍数来处理的。
.
以你现在的情况为例来说明，你定义了index，cnt，Udfil，Uqfil，Ud和Uq共6个单变量，后4个为float型，因此剩余64-(2+4*2)=54个word的空间。
你没有提供state结构体的定义，但我猜测它的大小应该是小于54个word，因此它会紧接着从0x880a开始分配，然后剩余一些“碎片”是浪费的。
但是ad的大小远远超出0x40，那么它是从0x8840开始分配内存的，直到下一个CLAsinTable也是从尾数为0x40的地址0x8b40开始。
00008800 _index
00008801 _cnt
00008802 _Udfil
00008804 _Uqfil
00008806 _Ud
00008808 _Uq
0000880a _state
00008840 _ad
00008b40 _CLAsinTable
.
当你使用数组定义且超出0x40的大小时，比如你屏蔽掉的部分，Udhis数组大小100，对应word数是200，它是大于0x40即64的，那么该数组将会占用4个独立的页，即它的第一个元素必然是放在尾数为0x40开始的地址，然后剩余的4*0x40-200=56个word的空间是浪费，紧接着又从下一个地址尾数为0x40倍数的空间分配Uqhis数组，同样是连续4个页。这样的结果就是，你有大量的空间像碎片一样被浪费，然后导致后面的CLAMathTable和scratchpad没有足够的空间来分配。
.
建议的做法是，像你现在一样将多个变量和数组放在一个结构体里，或者尽可能将数组定义在0x40以内。
                                                                         If a post answers your question, please mark it with the "verify answer" button.

非常感谢您的帮助，很细心的讲解！
以后我也会注意询问时整理好资料！
感谢！

有另外两点可能需要补充说明的：
1. 即便是结构体，它的内存分配所遵循的规则和数组也是一样的，也就是说会按照0x40的倍数进行分配，只是结构体可以把很多变量和数组捆绑在一起，因此用户可以尽可能使结构体的总大小在接近0x40倍数的范围，从而节省空间不浪费；
2. 上面提到的数组或结构体尽可能在0x40大小范围以内，应该纠正为在0x40倍数的大小范围内，当然目的还是尽可能少地产生“碎片”。
                                                                         If a post answers your question, please mark it with the "verify answer" button.

你好，我想咨询一个问题，28035定时器中断问题。
TI官方给的定时器0中断程序是
void InitCpuTimers(void)
[
/* 初始化CPU Timer 0 */
CpuTimer0.RegsAddr = &CpuTimer0Regs; // 初始化地址指针指向CPU定时器T0的寄存器CpuTimer0Regs
CpuTimer0Regs.PRD.all = 0xFFFFFFFF; // 初始化T0的周期寄存器 TIMER0PRD=0xFFFFFFFF
CpuTimer0Regs.TPR.all = 0; // 初始化T0的预分频寄存器 TIMER0TPR = 0(定时器的时钟与SYSCLKOUT相同)，即T0计数器每隔1个SYSCLKOUT减1。
CpuTimer0Regs.TPRH.all = 0;
CpuTimer0Regs.TCR.bit.TSS = 1; // T0计数器停止计数
CpuTimer0Regs.TCR.bit.TRB = 1; // 重载T0计数器：将周期寄存器中的值载入到定时器计数器中
CpuTimer0.InterruptCount = 0; // 复位T0定时器中断次数计数器 CpuTimer0.InterruptCount
]


void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
[
Uint32 PeriodInClocks;

/* 配置定时器周期寄存器 */
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
PeriodInClocks = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = PeriodInClocks - 1; // Counter decrements PRD+1 times each period

/* 配置定时器的预分频寄存器 */
Timer->RegsAddr->TPR.all = 0; // 定时器时钟频率Freq = SYSCLKOUT / (TDDRH:TDDR+1)。此处Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPRH.all = 0;

/* 配置定时器的控制寄存器 */
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 0;
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt

/* 清定时器的中断次数计数器 */
Timer->InterruptCount = 0;
]

如果我想设定100US中断一次，那么调用ConfigCpuTimer(&CpuTimer0, 60, 100);
我的问题是：如果我现在想让定时器0的中断频率与电网频率一致，电网频率假如是Freq,在50Hz左右波动，此时改如何设置CPUtimer0呢？

已在下面帖子回复。建议如下一样，新问题另起一帖，另外，还是麻烦尽量不要粘贴代码，上传附件更方便。
http://www.deyisupport.com/question_answer/microcontrollers/c2000/f/56/p/123433/343037.aspx#343037
                                                                         If a post answers your question, please mark it with the "verify answer" button.