请问一下，将C28设定为PWM输出控制电机，如何设置才能使PWM输出反向？

更改后的波形是什么样的？

你好，
是这样的，
正常设定CMPA值增加时，PWM输出的高电平宽度变小。
而将AQCTLA的设定反向时，CMPA增加，PWM输出的高电平宽度也是变小的。

你需要将ZRO和PRD也设置成反相。

你的程序修改是没错的。有种可能是你开启了死区设置，并且以EPWMB为基准，这样PWMA输出只会按照B通道设置。你可以把整个EPWM的所有寄存器设置发上来检查

原来的设定：
//EPMW Module 1 config
// Setup TBCLK
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
// EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions

 EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
 EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count


// // Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

EPwm1Regs.DBRED = EPWM_DB;
EPwm1Regs.DBFED = EPWM_DB;

反向的设定：

//EPMW Module 1 config
// Setup TBCLK
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
// EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

 EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR ; // Set PWM1A on event A, up count
 EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, down count



// // Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;

EPwm1Regs.DBRED = EPWM_DB;
EPwm1Regs.DBFED = EPWM_DB;

请帮忙检查！

EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
设置成这样，直接取反
                                                                        keep on studying

不行呢。
设置成这样EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
死区的前后顺序不正确。正常需要A延后B下降，但是这样设定变成A提前B下降了。

 Dear  Terry :
请问这样的配置要怎么修改！
还请帮忙！
谢谢！

只是想把电平取反的话，

这个不用修改，保持和原来一样
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET ; // Set PWM1A on event A, up count
 EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

只修改这个就可以了
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;

Terry:
可以了！
感谢！

学习了，最近刚好接触到