请问ePWM周期是多久？在什么时候更新？

本帖最后由 一只耳朵怪 于 2018-6-13 16:56 编辑

// Setup TBCLK   EPwm1Regs.TBPRD = EPWM1_tiMER_TBPRD;           // Set timer period 801 TBCLKs   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0   EPwm1Regs.TBCTR = 0x0000;                      // Clear counter      // Set Compare values   EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA;     // Set compare A value   EPwm1Regs.CMPB = EPWM1_MAX_CMPB;               // Set Compare B value      // Setup counter mode   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;   // Setup shadowing   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // Load on Zero   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;      // Set actions   EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;             // Set PWM1A on event A, up count   EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM1A on event A, down count   EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;             // Set PWM1B on event B, up count   EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;           // Clear PWM1B on event B, down count代码如上，若改变   EPwm1Regs.CMPA.half.CMPA 与   EPwm1Regs.CMPB的值，那么会在CTR=ZERO时将EPwm1Regs.CMPA.half.CMPA 与   EPwm1Regs.CMPB的值进行更新，问题是若改变EPwm1Regs.TBPRD 的值，会在什么时候更新？