请问仿真器重新上电后老是丢失系统时钟是为什么？如何解决？

xiangjun
你配置系统时钟源的时候选择的是什么，你可以重新烧程序，配置为内部时钟1。
Eric
                                                                         - ERIC

Eric
1.我在datasheet上没有找到配置时钟源的寄存器 是不是PLLSTS[OSCOFF] = 0是外部时钟源，PLLSTS[OSCOFF] = 1是内部时钟源
2.我用的是外部时钟源，如果配置成内部时钟源，是不是等时钟稳定后在配置成外部时钟源？

xiangjun,
你需要到芯片主页那儿去找 system control and interrupts user guide，里面才有所有详细的手册，datasheet只是一些参数而已。
系统上电启动默认是先用内部时钟，在main的最开始会进行系统初始化，sysctrlinit， 在DSP2803x_SysCtrl.c这个源文件。你在这里面切换到外部晶振就可以了。都是有相关函数给你切换的，不用你自己去配置寄存器。
下载controlSUITE。
Eric
                                                                         - ERIC

如果是main之前启用内部时钟的话 那还需要我配置吗？我用的就是void InitSysCtrl(void)函数   在TMS320x2833x, 2823x System Control and Interrupts Reference Guide里面查的资料

楼主的配置程序中都没用ELLOW和EDIS的？这样是改变不了受保护的寄存器的值的，如
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
建议参考controlsuite里面的F2803X的DSP2803X_SysCtrl.c。

Martin Yu
这是配置源代码：
void InitSysCtrl(void)
[
volatile Uint16 i;                        // General purpose Uint16
volatile int16 dummy;                    // General purpose volatile int16

    DisableDog();
    asm(" EALLOW");                        // Enable EALLOW protected register access
//#ifdef 1
//--- Memory Protection Configuration
    DevEmuRegs.PROTSTART = 0x0100;        // 写默认值来保护开始寄存器Write default value to protection start register
    DevEmuRegs.PROTRANGE = 0x00FF;        // 写默认值来保护类型寄存器Write default value to protection range register

//--- Configure the PLL
// Note: The DSP/BIOS configuration tool can also be used to initialize the PLL
// instead of doing the initialization here.

    while(SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
    [
        DelayUs(20);
        SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
    ]
    
    // Make sure the PLL is not running in limp mode
    if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1)
    [                                                    // PLL is not running in limp mode
        SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;                // Turn off missing clock detect before changing PLLCR
        SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;                // DIVSEL must be 0 or 1  (/4 CLKIN mode) before changing PLLCR
        SysCtrlRegs.PLLCR.bit.DIV = 0x000A;                // PLLx10/4 (because DIVSEL is /4)
   
        // Wait for PLL to lock.
        // During this time the CPU will run at OSCCLK/2 until the PLL is stable.
        // Once the PLL is stable the CPU will automatically switch to the new PLL value.
        // Code is not required to sit and wait for the PLL to lock.  However,
        // if the code does anything that is timing critical (e.g. something that
        // relies on the CPU clock frequency to be at speed), then it is best to wait
        // until PLL lock is complete.  The watchdog should be disabled before this loop
        // (e.g., as was done above), or fed within the loop.
        while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)        // Wait for PLLLOCKS bit to set
        [
            //SysCtrlRegs.WDKEY = 0x0055;                    // Service the watchdog while waiting
            //SysCtrlRegs.WDKEY = 0x00AA;                    //   in case the user enabled it.
        ]

        // After the PLL has locked, we are running in PLLx10/4 mode (since DIVSEL is /4).
        // We can now enable the missing clock detect circuitry, and also change DIVSEL
        // to /2.  In this example, I will wait a bit of time to let inrush currents settle,
        // and then change DIVSEL from /4 to /2.  This is only an example.  The amount of
        // time you need to wait depends on the power supply feeding the DSP (i.e., how much
        // voltage droop occurs due to the inrush currents, and how long it takes the
        // voltage regulators to recover).
        SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;                // Enable missing clock detect circuitry
        DelayUs(20/2);                                    // Wait 20 us (just an example).  Remember we're running
                                                        // at half-speed here, so divide function argument by 2.
        SysCtrlRegs.PLLSTS.bit.DIVSEL = 0x2;            // Change to /2 mode
    ]
    else
    [                                                    // PLL is running in limp mode
    // User should replace the below with a call to an appropriate function,
    // for example shutdown the system (since something is very wrong!).
        asm(" ESTOP0");
    ]
    
//#endif

   // Initialize the PLL control: PLLCR and DIVSEL
   // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
   //InitPll(DSP28_PLLCR,DSP28_DIVSEL);

//--- Configure the clocks
    SysCtrlRegs.HISPCP.all = 0x0000;        // Hi-speed periph clock prescaler, HSPCLK=SYSCLKOUT/1
    SysCtrlRegs.LOSPCP.all = 0x0000;        // Lo-speed periph clock prescaler, LOSPCLK=SYSCLKOUT/1

    SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1;    // GPIO input module is clocked
    SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;        // XINTF module is clocked
    SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1;        // SYSCLKOUT to DMA enabled
    SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1;    // SYSCLKOUT to CPU Timer2 enabled
    SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1;    // SYSCLKOUT to CPU Timer1 enabled
    SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1;    // SYSCLKOUT to CPU Timer0 enabled

    SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1;        // SYSCLKOUT to eQEP2 enabled
    SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1;        // SYSCLKOUT to eQEP1 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1;        // SYSCLKOUT to eCAP6 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1;        // SYSCLKOUT to eCAP5 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1;        // SYSCLKOUT to eCAP4 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1;        // SYSCLKOUT to eCAP3 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1;        // SYSCLKOUT to eCAP2 enabled
    SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1;        // SYSCLKOUT to eCAP1 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1;        // SYSCLKOUT to ePWM6 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1;        // SYSCLKOUT to ePWM5 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;        // SYSCLKOUT to ePWM4 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1;        // SYSCLKOUT to ePWM3 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;        // SYSCLKOUT to ePWM2 enabled
    SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;        // SYSCLKOUT to ePWM1 enabled
    
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;   // Enable TBCLK within the ePWM

    SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;        // SYSCLKOUT/2 to eCAN-B enabled
    SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;        // SYSCLKOUT/2 to eCAN-A enabled
    SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1;    // LSPCLK to McBSP-A enabled
    SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1;    // LSPCLK to McBSP-B enabled
    SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;        // LSPCLK to SCI-B enabled
    SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;        // LSPCLK to SCI-A enabled
    SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1;        // LSPCLK to SPI-A enabled
    SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1;        // LSPCLK to SCI-C enabled
    SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1;        // LSPCLK to I2C-A enabled
    SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;        // HSPCLK to ADC enabled
// The PCLKCR0.TBCLKSYNC bit is handled separately in InitEPwm() since
// it affects synchronization of the ePWM counters.

//--- Configure the low-power modes
    SysCtrlRegs.LPMCR0.all = 0x00FC;        // LPMCR0 set to default value

//--- Finish up
    asm(" EDIS");                        // Disable EALLOW protected register access

] // end InitSysCtrl()
寄存器肯定是写进去了，就是重新上电后SysCtrlRegs.PLLSTS.bit.MCLKSTS会置为1  导致无法在配置时钟  不知道为什么
quan

TI没人管了么？？？？

Xiangjun,
根据你的描述（仿真模式下正常），建议可以先检查下硬件方面，主要用示波器看下复位电路和晶振的信号是否正常。谢谢！