AM5728 MCASP2时钟MCASP2_ACLKX不能输出，请问是缺少配置还是配置有问题？

本帖最后由 一只耳朵怪 于 2018-6-4 09:13 编辑

下面是我在AM5728EVM开发板上，利用GPIO_LedBlink_evmAM572x_c66xExampleProject例程的工程和MCASP_Audio_evmAM572x_c66ExampleProject例程中void McASP2_Enable(void)改写的代码：
void McASP2_Enable(void)
[
//选取SYS_CLK1 20 MHz
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_SYS_REG,
CSL_CKGEN_PRM_CM_CLKSEL_SYS_REG_SYS_CLKSEL,
CSL_CKGEN_PRM_CM_CLKSEL_SYS_REG_SYS_CLKSEL_RESERVED);//20M
// Choose SYS_CLK1 (20 MHZ) as source for ABE_DPLL_SYS_CLK
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG,
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL,
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);
//Selects ABE_DPLL_SYS_CLK for ABE_DPLL_CLK
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_REF_REG,
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_REF_REG_CLKSEL,
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_REF_REG_CLKSEL_SEL_SYS_CLK);

// Reprogram ABE DPLL for 200 MHz output on DPLL_ABE_CLKOUTX2_M2 line //
// step 1: disable the PLL, if enabled (ex: via GEL)
while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE);
// step 2: modify Synthesized Clock Parameters - DPLL MULT & DIV
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT,
0x64);//M=100
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV,
0x13);//N=19
// step 3: Configure output clocks parameters - M2 = 1 M3 = 1
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS,
0x1);
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS,
0x1);
// step 4: Confirm that the PLL has locked
while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);
// McASP2 Module Control //
//选取 clkout2 Selects divided version of PER_ABE_X1_GFCLK //分频不能选
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG,
CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL,
CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_DPLL_ABE_CLKOUT);
//PER_ABE_X1_GFCLK DIV
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_REG,
CSL_CKGEN_PRM_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_REG_CLKSEL,
CSL_CKGEN_PRM_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_REG_CLKSEL_CLK_DIV_1);

//选取 PER_ABE_X1_GFCLK
//0x4A00 9860
HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG,
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG_CLKSEL_AUX_CLK,
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG_CLKSEL_AUX_CLK_SEL_PER_ABE_X1_GFCLK);
//禁用输入
//0x4A00 36F4
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX,
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_INPUTENABLE,
0x0);

// PAD IO Config for MCASP2 pins - ACLKX, AFSX, AXR0, AXR1//
//0x4A00 36F4
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX,
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_MUXMODE,
0x0);
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX,
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_MUXMODE,
0x0);
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR0,
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR0_MCASP2_AXR0_MUXMODE,
0x0);
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR1,
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR1_MCASP2_AXR1_MUXMODE,
0x0);
//MCASP2 使能
HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG,
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG_MODULEMODE,
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG_MODULEMODE_ENABLE);
while (HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG) !=
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP2_CLKCTRL_REG_MODULEMODE_ENABLE) ;
//禁用XREF_CLK0
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0,
CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE,
0x0); // 0x0: Receive mode is disabled
//clkout2 pinmux
//0x4A00 3694
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0,
CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE,
0x9); //0x9:
//clkout2开门
//0x4A00 86B0
HW_WR_FIELD32(CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG,
CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK,
CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN);
]
代码简介：选取CLK1_20M,进入锁相环，clkout2正确输出100M，但是MCASP2_ACLKX没有反应
请问我的问题出现在哪里？是缺少配置还是配置有问题