完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
你好,
我在Xilinx Vivado中遇到了累加器(Add)的问题。 我用VHDL编写了程序。 实施时会出现以下错误: 信息:[DRC 23-20]规则违规(AVAL-4)enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CE·D_CEAD_RSTD_GND - fpAccOne_Stage1 / U0 / i_synth / ACCUM_OP.OP / g_accum_split [0] .g_dsp_split.i_adder / DSP:DSP48E1未使用D端口(USE_DPORT = FALSE) 。 为了改善功耗特性,将DREG和ADREG设置为1,将CED,CEAD和RSTD连接到逻辑'0'。 如何在Xilinx IP中纠正此规则违规。 我的组件: 组件fpAcc 港口 ( aclk:IN STD_LOGIC; aclken:IN STD_LOGIC; aresetn:IN STD_LOGIC; s_axis_a_tvalid:IN STD_LOGIC; s_axis_a_tdata:IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tlast:IN STD_LOGIC; s_axis_operation_tvalid:IN STD_LOGIC; s_axis_operation_tdata:IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_result_tvalid:OUT STD_LOGIC; m_axis_result_tdata:OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tlast:OUT STD_LOGIC ); 结束组成部分; 实例: fpAccOne_Stage1:fpAcc 港口地图( aclk => clockIn, aclken =>'1', aresetn => aresetn_Stage1, s_axis_a_tvalid => s_axis_a_tvalid_Stage1, s_axis_a_tdata => inA_Stage1, s_axis_a_tlast => s_axis_a_tlast_Stage1, s_axis_operation_tvalid => s_axis_operation_tvalid_Stage1, s_axis_operation_tdata =>“00000000”, m_axis_result_tvalid => m_axis_result_tvalid_Stage1, m_axis_result_tdata => outA_Stage1, m_axis_result_tlast => m_axis_result_tlast_Stage1 ); 我已将值指定为 s_axis_operation_tvalid_Stage1 我是否正确分配了 对于消息:将DREG和ADREG设置为'1',将CED,CEAD和RSTD连接到逻辑'0',如何使用IP目录/ IP的重新声明来分配这些值? 我在Verilog看到了对类似问题的回复: https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/m-p/549620#M11094 但我没有得到任何答案。 以上来自于谷歌翻译 以下为原文 Hello, I have a problem with the Accumulator (Add) in Xilinx Vivado. I have written the program in VHDL. The following error is coming up while implementation: INFO: [DRC 23-20] Rule violation (AVAL-4) enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND - fpAccOne_Stage1/U0/i_synth/ACCUM_OP.OP/g_accum_split[0].g_dsp_split.i_adder/DSP: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. How can I rectify this rule violation in Xilinx IP. My component : COMPONENT fpAcc PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC );END COMPONENT; Instantiation: fpAccOne_Stage1 : fpAcc PORT MAP ( aclk => clockIn, aclken => '1', aresetn => aresetn_Stage1, s_axis_a_tvalid => s_axis_a_tvalid_Stage1, s_axis_a_tdata => inA_Stage1, s_axis_a_tlast => s_axis_a_tlast_Stage1, s_axis_operation_tvalid => s_axis_operation_tvalid_Stage1, s_axis_operation_tdata => "00000000", m_axis_result_tvalid => m_axis_result_tvalid_Stage1, m_axis_result_tdata => outA_Stage1, m_axis_result_tlast => m_axis_result_tlast_Stage1 ); I have assigned the values as s_axis_operation_tvalid_Stage1 <= '0';s_axis_a_tlast_Stage1 <= '0';aresetn_Stage1 <= '0'; Did I assign correctly. For the message : set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0', how to assign these values using IP Catalog/Recostumization of IP? I have seen the reply to a similar question in Verilog here: https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/m-p/549620#M11094 but I did not get any answer. |
|
相关推荐
3个回答
|
|
http://www.xilinx.com/support/answers/56354.html
上述链接中提出的解决方案运行良好。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 http://www.xilinx.com/support/answers/56354.html The solution suggested in the above link worked well. View solution in original post |
|
|
|
检查这些链接https://forums.xilinx.com/t5/Inmplementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/td-p/549620https://
forums.xilinx.com/t5/DSP-and-Video/Drc-23-20-Rule-violation-AVAL-4/td-p/675682http://www.xilinx.com/support/answers/56354.html 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 check these links https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/td-p/549620 https://forums.xilinx.com/t5/DSP-and-Video/Drc-23-20-Rule-violation-AVAL-4/td-p/675682 http://www.xilinx.com/support/answers/56354.htmlThanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
|
|
|
http://www.xilinx.com/support/answers/56354.html
上述链接中提出的解决方案运行良好。 以上来自于谷歌翻译 以下为原文 http://www.xilinx.com/support/answers/56354.html The solution suggested in the above link worked well. |
|
|
|
只有小组成员才能发言,加入小组>>
2165 浏览 7 评论
2608 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2080 浏览 9 评论
3152 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2197 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
429浏览 1评论
1528浏览 1评论
在使用xc5vsx95T时JTAG扫片不成功,测量TDO无信号输出
2180浏览 0评论
511浏览 0评论
1644浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-4-27 10:55 , Processed in 1.032036 second(s), Total 47, Slave 41 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号