VHDL编写程序出现错误

你好，
我在Xilinx Vivado中遇到了累加器（Add）的问题。
我用VHDL编写了程序。
实施时会出现以下错误：
信息：[DRC 23-20]规则违规（AVAL-4）enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CE·D_CEAD_RSTD_GND  -  fpAccOne_Stage1 / U0 / i_synth / ACCUM_OP.OP / g_accum_split [0] .g_dsp_split.i_adder / DSP：DSP48E1未使用D端口（USE_DPORT = FALSE）
。
为了改善功耗特性，将DREG和ADREG设置为1，将CED，CEAD和RSTD连接到逻辑'0'。
如何在Xilinx IP中纠正此规则违规。
我的组件：
组件fpAcc
港口 （
aclk：IN STD_LOGIC;
aclken：IN STD_LOGIC;
aresetn：IN STD_LOGIC;
s_axis_a_tvalid：IN STD_LOGIC;
s_axis_a_tdata：IN STD_LOGIC_VECTOR（31 DOWNTO 0）;
s_axis_a_tlast：IN STD_LOGIC;
s_axis_operation_tvalid：IN STD_LOGIC;
s_axis_operation_tdata：IN STD_LOGIC_VECTOR（7 DOWNTO 0）;
m_axis_result_tvalid：OUT STD_LOGIC;
m_axis_result_tdata：OUT STD_LOGIC_VECTOR（31 DOWNTO 0）;
m_axis_result_tlast：OUT STD_LOGIC
）;
结束组成部分;
实例：
fpAccOne_Stage1：fpAcc
港口地图（
aclk => clockIn，
aclken =>'1'，
aresetn => aresetn_Stage1，
s_axis_a_tvalid => s_axis_a_tvalid_Stage1，
s_axis_a_tdata => inA_Stage1，
s_axis_a_tlast => s_axis_a_tlast_Stage1，
s_axis_operation_tvalid => s_axis_operation_tvalid_Stage1，
s_axis_operation_tdata =>“00000000”，
m_axis_result_tvalid => m_axis_result_tvalid_Stage1，
m_axis_result_tdata => outA_Stage1，
m_axis_result_tlast => m_axis_result_tlast_Stage1
）;
我已将值指定为
s_axis_operation_tvalid_Stage1
我是否正确分配了
对于消息：将DREG和ADREG设置为'1'，将CED，CEAD和RSTD连接到逻辑'0'，如何使用IP目录/ IP的重新声明来分配这些值？
我在Verilog看到了对类似问题的回复：
https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/m-p/549620#M11094
但我没有得到任何答案。



以下为原文

Hello,
I have a problem with the Accumulator (Add) in Xilinx Vivado.
I have written the program in VHDL.

The following error is coming up while implementation:
INFO: [DRC 23-20] Rule violation (AVAL-4) enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND - fpAccOne_Stage1/U0/i_synth/ACCUM_OP.OP/g_accum_split[0].g_dsp_split.i_adder/DSP: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.

How can I rectify this rule violation in Xilinx IP.

My component :

COMPONENT fpAcc  PORT (    aclk : IN STD_LOGIC;    aclken : IN STD_LOGIC;    aresetn : IN STD_LOGIC;    s_axis_a_tvalid : IN STD_LOGIC;    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);    s_axis_a_tlast : IN STD_LOGIC;    s_axis_operation_tvalid : IN STD_LOGIC;    s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);    m_axis_result_tvalid : OUT STD_LOGIC;    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);    m_axis_result_tlast : OUT STD_LOGIC  );END COMPONENT;
Instantiation:

fpAccOne_Stage1 : fpAcc  PORT MAP (    aclk => clockIn,    aclken => '1',    aresetn => aresetn_Stage1,    s_axis_a_tvalid => s_axis_a_tvalid_Stage1,        s_axis_a_tdata => inA_Stage1,    s_axis_a_tlast => s_axis_a_tlast_Stage1,    s_axis_operation_tvalid => s_axis_operation_tvalid_Stage1,    s_axis_operation_tdata => "00000000",    m_axis_result_tvalid => m_axis_result_tvalid_Stage1,    m_axis_result_tdata => outA_Stage1,    m_axis_result_tlast => m_axis_result_tlast_Stage1  );  I have assigned the values as
s_axis_operation_tvalid_Stage1 <= '0';s_axis_a_tlast_Stage1 <= '0';aresetn_Stage1 <= '0';                                    
Did I assign correctly.

For the message : set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0', how to assign these values using IP Catalog/Recostumization of IP?

I have seen the reply to a similar question in Verilog here:
https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-AVAL-4-enum-USE-DPORT-FALSE-enum-DREG/m-p/549620#M11094

but I did not get any answer.