嗨，
1）在发生这种情况时检查时钟信号的完整性，因为使用多个IO bank可能会增加IO时钟的噪声
2）检查电源线的电源完整性。
3）检查是否有一个克隆电路，使数据与眼睛中心对齐。
4）探测时钟与数据输入，以查看是否得到了不正确的对齐，并且错过了一些数据位。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。
以上来自于谷歌翻译
以下为原文
Hi,
1) Check the clock signal integrity when this is happenning, since the usage of multiple IO banks may increase the noise on the IO clock
2) Check the power integrity for the power lines.
3) Check if you have a clibration circuit to make the data aigned to the centre of the eye.
4) Probe the Clock vs data input to see if you are getting the improper alignment and some data bits are being missed.
Thanks,
Anirudh
PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
嗨，
1）在发生这种情况时检查时钟信号的完整性，因为使用多个IO bank可能会增加IO时钟的噪声
2）检查电源线的电源完整性。
3）检查是否有一个克隆电路，使数据与眼睛中心对齐。
4）探测时钟与数据输入，以查看是否得到了不正确的对齐，并且错过了一些数据位。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。
以上来自于谷歌翻译
以下为原文
Hi,
1) Check the clock signal integrity when this is happenning, since the usage of multiple IO banks may increase the noise on the IO clock
2) Check the power integrity for the power lines.
3) Check if you have a clibration circuit to make the data aigned to the centre of the eye.
4) Probe the Clock vs data input to see if you are getting the improper alignment and some data bits are being missed.
Thanks,
Anirudh
PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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